Does AES64DSM use floating-point or vector registers?
No. These scalar crypto extension instructions use integer X registers.
AES64DSM
RISC-V AES64DSM Instruction Details
Instruction ManualR-typeAES middle-round decrypt (RV64): two 64-bit source registers represent the full state and apply inverse ShiftRows/SubBytes/MixColumns
Instruction Syntax
aes64dsm rd, rs1, rs2
Syntax is rd, rs1, rs2; there is no immediate operand. Registers select x0–x31 or ABI names, with no rs3.
32-bit OP encoding: funct7=0011111, funct3=000, opcode=0110011.
RV64 only, requiring Zknd (also included in Zkn/Zk). rs1/rs2 supply the full 128-bit state; inverse ShiftRows, per-byte inverse S-box, and InvMixColumns on two 32-bit words produce one 64-bit output half, without implicit round-key XOR.
x0 sources are zero and rd=x0 discards writeback; overlap reads pre-execution source values, and equal sources have equal values. This instruction must have data-independent execution latency.
ZkndCrypto & Security
Instruction Behavior
aes64dsm is an RV64 AES decrypt middle-round instruction in Zknd. It uses rs1 and rs2 as two 64-bit source registers representing the full 128-bit AES state, applies Inverse ShiftRows, inverse SubBytes, and InvMixColumns, and writes half of the next-round output to rd. The full 128-bit output is normally produced by executing the official paired instruction with reversed source-register order; round-key XOR is not implicitly performed by this AES64 round instruction.
AES64DSM Decode And Execute Animation
Bounded teaching inputs follow the local official ISA formulas; this does not model a complete AES round, round-key XOR, or microarchitecture.
aes64dsm
Execution Context
XLEN is fixed at 64; rs1 and rs2 jointly represent the complete 128-bit state. A destination that is not a source starts at 0; sources are read before writeback.
fixed funct7
source state
source state
fixed
destination
OP
31..25
0011111
24..20
rs2=x12
19..15
rs1=x11
14..12
000
11..7
rd=x10
6..0
0110011
Execution Data Path
rs1[63:0]
0x0011223344556677
rs2[63:0]
0x8899AABBCCDDEEFF
aes_rv64_shiftrows_inv
0xCC99663300DDAA77
inverse SubBytes
0x27F9D36652C96202
two aes_mixcolumn_inv words
0x460A644350878DA1
Current Step
Decode AES64 fixed OP fields
funct7=0011111, funct3=000, and OP=0110011; this encoding is RV64-only.
encoding: 0x3EC58533
syntax: aes64dsm a0(x10), a1(x11), a2(x12)
syntax: aes64dsm a0(x10), a1(x11), a2(x12)
Architectural Result
a0(x10) = 0x0000000000000000
This animation shows only official ISA fields and architectural state, not a particular CPU pipeline, cache, or timing implementation.
Quick Understanding & Search Notes
AES64DSM reads two 64-bit state halves from rs1/rs2, applies inverse ShiftRows and a per-byte inverse S-box, then InvMixColumns on each 32-bit word, and writes one 64-bit result. Preserve the original sources and reverse their order for the other half; round-key XOR is separate.
RV64 instruction: rs1/rs2 together represent the full AES state, and the instruction produces half of the next-round output; compute the other half with reversed source-register order.
Operands use integer X registers; this instruction must have execution latency independent of its input data values.
This instruction is defined only for RV64 and requires Zknd; it includes InvMixColumns, which the final-round aes64ds omits.
Common Usage Scenarios
Crypto & Security
RV64 Zknd, a1=0x0011223344556677 and a2=0x8899AABBCCDDEEFF: inverse ShiftRows gives 0xCC99663300DDAA77; per-byte inverse S-box followed by InvMixColumns gives a0=0x460A644350878DA1. Preserve the original sources and reverse their order for the other half.
Data Protection
RV64 Zknd, a1=0x0011223344556677 and a2=0x8899AABBCCDDEEFF: inverse ShiftRows gives 0xCC99663300DDAA77; per-byte inverse S-box followed by InvMixColumns gives a0=0x460A644350878DA1. Preserve the original sources and reverse their order for the other half.
Pre-Use Checklist
Syntax Check
- Syntax is rd, rs1, rs2; there is no immediate operand. Registers select x0–x31 or ABI names, with no rs3.
- 32-bit OP encoding: funct7=0011111, funct3=000, opcode=0110011.
Semantic Check
- RV64 only, requiring Zknd (also included in Zkn/Zk). rs1/rs2 supply the full 128-bit state; inverse ShiftRows, per-byte inverse S-box, and InvMixColumns on two 32-bit words produce one 64-bit output half, without implicit round-key XOR.
- x0 sources are zero and rd=x0 discards writeback; overlap reads pre-execution source values, and equal sources have equal values. This instruction must have data-independent execution latency.
Pitfalls / Common Confusions
RV64 only; this AES64 form is not available on RV32.
rs1 and rs2 are the two 64-bit halves of the current AES state; do not describe rs2 as a fixed round-key operand.
AES64DSM middle rounds include InvMixColumns; AES64DS final rounds do not.
One execution produces only half of the 128-bit state output; compute the other half using the official reversed source-register order.
FAQ
Is AES64DSM a complete algorithm implementation?
No. It performs one architecturally defined AES half-state step; software still combines instructions and round keys in algorithm order.