Does AES64IM use floating-point or vector registers?
No. These scalar crypto extension instructions use integer X registers.
AES64IM
RISC-V AES64IM Instruction Details
Instruction ManualI-typeApply AES InvMixColumns to 64-bit half-block in rs1 (for equivalent inverse key schedule)
Instruction Syntax
aes64im rd, rs1
Operand Breakdown
rd: receives the 64-bit value packing the two InvMixColumns results.
rs1: one register packs two 32-bit AES state columns; its low and high 32-bit words each enter InvMixColumns.
Bits 31..20 are fixed to 001100000000. This is an encoding constant, not an assembly immediate and not a 12-bit signed value to sign-extend.
ZkndCrypto & Security
Instruction Behavior
aes64im is a Zknd auxiliary instruction (RV64 only). It applies AES InvMixColumns to two state columns packed in one 64-bit register and writes the result to rd. It helps create the decryption key schedule according to the equivalent inverse-cipher construction; it performs neither SBox nor round-key XOR.
AES64IM Decode And Execute Animation
Bounded teaching inputs follow the local official ISA formulas; this does not model a complete AES algorithm or microarchitecture.
aes64im
Execution Context
XLEN is fixed at 64; this AES64 form is not defined for RV32. A destination that is not a source starts at 0; sources are read before writeback.
fixed
fixed x0
source
fixed
destination
OP-IMM
31..25
0011000
24..20
00000
19..15
rs1=x11
14..12
001
11..7
rd=x10
6..0
0010011
Execution Data Path
rs1[63:32]
0x11223344
rs1[31:0]
0x55667788
InvMixColumns high:low
0x6195CB7B:0x8A632B0E
Current Step
Decode fixed fields and operands
AES64IM is defined only for RV64; fixed fields, integer-register fields, and the OP/OP-IMM major opcode identify this encoding.
encoding: 0x30059513
syntax: aes64im a0(x10), a1(x11)
syntax: aes64im a0(x10), a1(x11)
Architectural Result
a0(x10) = 0x0000000000000000
This animation shows only official ISA fields and architectural state, not a particular CPU pipeline, cache, or timing implementation.
Quick Understanding & Search Notes
AES64IM is a Zknd scalar cryptography instruction for AES inverse MixColumns for key schedule.
An RV64 instruction that applies InvMixColumns to two AES columns packed in one 64-bit register for equivalent inverse-cipher key schedule generation.
Scalar crypto instructions use integer X registers, and the official spec requires the relevant crypto instructions to be implemented with data-independent execution latency.
aes64* forms are defined only for RV64.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «aes64im a0, a1».
Key Schedule
Understand this scenario with real code like «aes64im a0, a1».
Pre-Use Checklist
Syntax Check
- RV64 only; register operands select integer x0–x31, with no rs3. Verify availability of the Zkne or Zknd extension listed on this page.
- There is no assembly immediate; fixed encoding fields undergo no arithmetic-immediate sign extension.
Semantic Check
- aes64im is a Zknd auxiliary instruction (RV64 only). It applies AES InvMixColumns to two state columns packed in one 64-bit register and writes the result to rd. It helps create the decryption key schedule according to the equivalent inverse-cipher construction; it performs neither SBox nor round-key XOR.
- Overlapping operands read source values before writeback; one source register has one value, x0 is always zero, and writes to x0 are discarded.
Pitfalls / Common Confusions
RV64 only.
Only performs InvMixColumns; no S-Box or round-key XOR involved.
Used for equivalent inverse key schedule derivation, not data decryption itself.
FAQ
Is AES64IM a complete algorithm implementation?
No. It performs the architecturally defined InvMixColumns step for two AES state columns; software still constructs the complete key schedule.