Does AES64IM use floating-point or vector registers?
No. These scalar crypto extension instructions use integer X registers.
AES64IM
RISC-V AES64IM Instruction Details
Instruction ManualR-typeApply AES InvMixColumns to 64-bit half-block in rs1 (for equivalent inverse key schedule)
Instruction Syntax
aes64im rd, rs1
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZkndCrypto & Security
Instruction Encoding
31..20
imm[11:0]
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
AES64IM uses opcode 0010011 (0x13), funct3 001, funct7 0011000. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.
Format: I-type
opcode: 0010011 (0x13)
funct3: 001 (0x1)
funct7: 0011000 (0x18)
Instruction Behavior
aes64im is a Zknd auxiliary instruction (RV64 only). It applies AES InvMixColumns to the low 64 bits of rs1, writing to rd. Primarily used to compute the Equivalent Inverse Cipher Key Schedule: transforming encrypt round keys via InvMixColumns so decrypt can reuse the same round-function structure. No round-key XOR is involved.
Quick Understanding & Search Notes
AES64IM is a Zknd scalar cryptography instruction for AES inverse MixColumns for key schedule. This page is checked against the official scalar crypto extension, avoiding confusion among round functions, key schedule steps, and operand sources.
An RV64 instruction that applies InvMixColumns to two AES columns packed in one 64-bit register for equivalent inverse-cipher key schedule generation.
Scalar crypto instructions use integer X registers, and the official spec requires the relevant crypto instructions to be implemented with data-independent execution latency.
aes64* forms are defined only for RV64.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «aes64im a0, a1».
Key Schedule
Understand this scenario with real code like «aes64im a0, a1».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
RV64 only.
Only performs InvMixColumns; no S-Box or round-key XOR involved.
Used for equivalent inverse key schedule derivation, not data decryption itself.
FAQ
Is AES64IM a complete algorithm implementation?
No. It is a low-level step from AES, SHA, SM3, or SM4; software still combines instructions with the algorithm schedule, round constants, or round keys.