AES64KS2

RISC-V AES64KS2 Instruction Details

Instruction ManualR-type

AES key schedule step 2 (RV64): combine rs1 and rs2 to produce next round key (AES-192/256)

Instruction Syntax

aes64ks2 rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZkndZkneCrypto & Security

Instruction Behavior

aes64ks2 is the AES key schedule instruction for Zknd/Zkne (RV64 only). It combines intermediate key states from rs1 and rs2 to produce either the upper 64 bits of the next round key or the next round-key state. Used for AES-192 and AES-256 key expansion. AES-128 does not need this instruction (aes64ks1i alone suffices). For AES-192/256, aes64ks1i and aes64ks2 are used alternately.

Quick Understanding & Search Notes

AES64KS2 is a Zknd/Zkne scalar cryptography instruction for AES key schedule XOR step. This page is checked against the official scalar crypto extension, avoiding confusion among round functions, key schedule steps, and operand sources.

An RV64 instruction for the additional key-word XOR combination step in the AES key schedule.
Scalar crypto instructions use integer X registers, and the official spec requires the relevant crypto instructions to be implemented with data-independent execution latency.
aes64* forms are defined only for RV64.

Common Usage Scenarios

Crypto & Security

Understand this scenario with real code like «aes64ks2 a0, a1, a2».

Key Schedule

Understand this scenario with real code like «aes64ks2 a0, a1, a2».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

RV64 only. AES-128 does not need this instruction.
AES-192/256 key expansion uses aes64ks1i and aes64ks2 alternately.
Must follow the correct rcon sequence and round-key ordering when paired with aes64ks1i.

FAQ

Does AES64KS2 use floating-point or vector registers?

No. These scalar crypto extension instructions use integer X registers.

Is AES64KS2 a complete algorithm implementation?

No. It is a low-level step from AES, SHA, SM3, or SM4; software still combines instructions with the algorithm schedule, round constants, or round keys.