Does AES64KS2 use floating-point or vector registers?
No. These scalar crypto extension instructions use integer X registers.
AES64KS2
RISC-V AES64KS2 Instruction Details
Instruction ManualR-typeAES key schedule step 2 (RV64): combine rs1 and rs2 with two fixed 32-bit XOR formulas
Instruction Syntax
aes64ks2 rd, rs1, rs2
Operand Breakdown
rd: receives w1:w0, with w0 in the low 32 bits and w1 in the high 32 bits.
rs1: supplies only rs1[63:32]; rs1[31:0] does not participate in this operation.
rs2: rs2[31:0] combines with rs1[63:32] to form w0; rs2[63:32] then XORs with w0 to form w1.
ZkndZkneCrypto & Security
Instruction Behavior
aes64ks2 is an RV64 AES key-schedule instruction shared by Zknd and Zkne. It computes w0 = rs1[63:32] XOR rs2[31:0], then w1 = w0 XOR rs2[63:32], and writes w1:w0 to rd.
AES64KS2 Decode And Execute Animation
Bounded teaching inputs follow the local official ISA formulas; this does not model a complete AES algorithm or microarchitecture.
aes64ks2
Execution Context
XLEN is fixed at 64; this AES64 form is not defined for RV32. A destination that is not a source starts at 0; sources are read before writeback.
fixed
source
source
fixed
destination
OP
31..25
0111111
24..20
rs2=x12
19..15
rs1=x11
14..12
000
11..7
rd=x10
6..0
0110011
Execution Data Path
rs1[63:32]
0x11223344
w0
0xF4D4345C
w1
0x5566F788
Current Step
Decode fixed fields and operands
AES64KS2 is defined only for RV64; fixed fields, integer-register fields, and the OP/OP-IMM major opcode identify this encoding.
encoding: 0x7EC58533
syntax: aes64ks2 a0(x10), a1(x11), a2(x12)
syntax: aes64ks2 a0(x10), a1(x11), a2(x12)
Architectural Result
a0(x10) = 0x0000000000000000
This animation shows only official ISA fields and architectural state, not a particular CPU pipeline, cache, or timing implementation.
Quick Understanding & Search Notes
AES64KS2 is a Zknd/Zkne scalar cryptography instruction for AES key schedule XOR step.
An RV64 instruction for the additional key-word XOR combination step in the AES key schedule.
Scalar crypto instructions use integer X registers, and the official spec requires the relevant crypto instructions to be implemented with data-independent execution latency.
aes64* forms are defined only for RV64.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «aes64ks2 a0, a1, a2».
Key Schedule
Understand this scenario with real code like «aes64ks2 a0, a1, a2».
Pre-Use Checklist
Syntax Check
- RV64 only; register operands select integer x0–x31, with no rs3. Verify availability of the Zkne or Zknd extension listed on this page.
- There is no assembly immediate; fixed encoding fields undergo no arithmetic-immediate sign extension.
Semantic Check
- aes64ks2 is an RV64 AES key-schedule instruction shared by Zknd and Zkne. It computes w0 = rs1[63:32] XOR rs2[31:0], then w1 = w0 XOR rs2[63:32], and writes w1:w0 to rd.
- Overlapping operands read source values before writeback; one source register has one value, x0 is always zero, and writes to x0 are discarded.
Pitfalls / Common Confusions
RV64 only.
aes64ks2 reads only rs1[63:32]; rs2[31:0] and rs2[63:32] feed w0 and w1 respectively.
The low 32 bits of rd are w0 and the high 32 bits are w1.
FAQ
Is AES64KS2 a complete algorithm implementation?
No. It performs one architecturally defined AES key-word XOR substep; software still combines instructions in algorithm order.