Does AES64KS1I use floating-point or vector registers?
No. These scalar crypto extension instructions use integer X registers.
AES64KS1I
RISC-V AES64KS1I Instruction Details
Instruction ManualI-typeAES key schedule step 1 (RV64): rnum selects a round constant for a conditional rotation and SubWord of rs1[63:32]
Instruction Syntax
aes64ks1i rd, rs1, rnum
Operand Breakdown
rd: receives the key-schedule word duplicated into both 32-bit halves.
rs1: supplies only rs1[63:32]; rs1[31:0] does not participate in this operation.
rnum: the four-bit round number in bits 23..20. Values 0x0..0xA are legal; 0xB..0xF are reserved encodings and cause an illegal-instruction exception. rnum=0xA does not rotate or call Rcon.
ZkndZkneCrypto & Security
Instruction Behavior
aes64ks1i is an RV64 AES key-schedule instruction shared by Zknd and Zkne. It takes rs1[63:32]; for rnum=0x0..0x9 it selects a round constant, rotates that word right by 8, then applies SubWord. rnum=0xA does not rotate and this AES-256 case does not call Rcon. The resulting word is copied to both 32-bit halves of rd. rnum=0xB..0xF is reserved and causes an illegal-instruction exception.
AES64KS1I Decode And Execute Animation
Bounded teaching inputs follow the local official ISA formulas; this does not model a complete AES algorithm or microarchitecture.
aes64ks1i
Execution Context
XLEN is fixed at 64; this AES64 form is not defined for RV32.
fixed
round number
source
fixed
destination
OP-IMM
31..24
00110001
23..20
rnum=1
19..15
rs1=x11
14..12
001
11..7
rd=x10
6..0
0010011
Execution Data Path
rs1[63:32]
0x11223344
conditional ror32
0x44112233
SubWord XOR Rcon
0x1B8293C1
Current Step
Decode fixed fields and operands
AES64KS1I is defined only for RV64; rnum occupies bits 23..20; 0x0..0xA is legal and 0xB..0xF does not decode as this instruction.
encoding: 0x31159513
syntax: aes64ks1i a0(x10), a1(x11), 1
syntax: aes64ks1i a0(x10), a1(x11), 1
Architectural Result
a0(x10) = 0x1B8293C11B8293C1
This animation shows only official ISA fields and architectural state, not a particular CPU pipeline, cache, or timing implementation.
Quick Understanding & Search Notes
AES64KS1I is a Zknd/Zkne scalar cryptography instruction for AES key schedule S-box/round-constant step. This page is checked against the official scalar crypto extension, avoiding confusion among round functions, key schedule steps, and operand sources.
An RV64 instruction for the rotate, SubBytes, and round-constant step of the AES key schedule; rnum is valid for 0x0..0xA and 0xB..0xF are reserved.
Scalar crypto instructions use integer X registers, and the official spec requires the relevant crypto instructions to be implemented with data-independent execution latency.
aes64* forms are defined only for RV64.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «aes64ks1i a0, a1, 1».
Key Schedule
Understand this scenario with real code like «aes64ks1i a0, a1, 1».
Pre-Use Checklist
Syntax Check
- Verify the immediate field is within the valid range.
- Confirm source register rs1 points to the correct operand.
Semantic Check
- Check if the immediate sign-extension matches expectations.
- Ensure the result register rd has a clear purpose.
Pitfalls / Common Confusions
RV64 only. rnum is encoded in four bits, but only 0x0..0xA are legal; 0xB..0xF are reserved.
rnum=0xA does not rotate; every other legal rnum rotates rs1[63:32] right by 8 first.
Both 32-bit halves of the result are equal; rs1[31:0] is not preserved directly.
FAQ
Is AES64KS1I a complete algorithm implementation?
No. It performs one architecturally defined AES key-schedule substep; software still combines instructions in algorithm order.