Does AES64KS1I use floating-point or vector registers?
No. These scalar crypto extension instructions use integer X registers.
AES64KS1I
RISC-V AES64KS1I Instruction Details
Instruction ManualR-typeAES key schedule step 1 (RV64): SubWord+RotWord on rs1 with rcon round constant, write to rd
Instruction Syntax
aes64ks1i rd, rs1, rcon
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZkndZkneCrypto & Security
Instruction Behavior
aes64ks1i is the AES key schedule instruction for Zknd/Zkne (RV64 only). It takes the previous round-key state in rs1 (64 bits) and a 4-bit immediate rcon (round constant), performs SubWord (S-Box on the most-significant word) and RotWord (rotate word), XORs with rcon, writing to rd. For AES-128, this alone completes one round of key expansion; for AES-192/256, aes64ks2 is also needed.
Quick Understanding & Search Notes
AES64KS1I is a Zknd/Zkne scalar cryptography instruction for AES key schedule S-box/round-constant step. This page is checked against the official scalar crypto extension, avoiding confusion among round functions, key schedule steps, and operand sources.
An RV64 instruction for the rotate, SubBytes, and round-constant step of the AES key schedule; rnum is valid for 0x0..0xA and 0xB..0xF are reserved.
Scalar crypto instructions use integer X registers, and the official spec requires the relevant crypto instructions to be implemented with data-independent execution latency.
aes64* forms are defined only for RV64.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «aes64ks1i a0, a1, 1».
Key Schedule
Understand this scenario with real code like «aes64ks1i a0, a1, 1».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
RV64 only. rcon is a 4-bit immediate (round constant).
AES-128 needs only this per round; AES-192/256 also needs aes64ks2.
Key schedule order must match the AES rcon sequence (rcon[i] = {02}^{i-1}).
FAQ
Is AES64KS1I a complete algorithm implementation?
No. It is a low-level step from AES, SHA, SM3, or SM4; software still combines instructions with the algorithm schedule, round constants, or round keys.