How is the offset written for c.flwsp?
Use a byte offset from 0 through 252 in multiples of 4. offset=16 adds 16 bytes without modifying the base.
C.FLWSP
RISC-V C.FLWSP Instruction Details
Instruction ManualCI-formatRV32FC 16-bit CI floating-point load, transferring 32 bits; base is x2/sp.
Instruction Syntax
c.flwsp fd, offset(sp)
The 5-bit fd field selects f0–f31; the base is fixed x2/sp. f0 is not integer zero.
offset is already an unsigned byte offset: 0–252, in multiples of 4, with 2 implied zero low bits. Do not scale it again.
RV32FC, floating-point state enabled, access permitted; load 32 raw bits, with upper bits set to ones when FLEN is wider.
Address is base plus offset, wrapping at XLEN. Natural alignment raises no address-misaligned exception; misaligned outcomes are EEI-defined and an exception is not shown as a completed access.
CFCompressed Instruction
Related Search Terms
Instruction Behavior
RV32FC: add an unsigned byte offset (0–252, multiples of 4) to x2/sp. On completion, load 32 memory bits into fd.
C.FLWSP Decode & Execute Animation
Shows only manual-defined 16-bit fields, operands, and ISA-visible results; it does not model a pipeline, cache, timing, or an implementation's memory-fault handling.
c.flwsp,(sp)
Execution context
RV32FC; floating-point state enabled, ordinary address calculation (no address-transforming extensions), and memory bits already assembled using the environment's byte order.
This load teaching environment fixes FLEN=32. With a wider FLEN, the 32-bit transfer writes ones to the upper f-register bits, creating a valid NaN-boxed value.
Naturally aligned accesses do not raise an address-misaligned exception; whether a misaligned access completes or raises an address-misaligned/access-fault exception is EEI-defined. This control displays only the selected outcome branch.
x2/sp = 0x00001000; memory 32-bit pattern = 0x3F800000. -> 0x00001010 -> f0 = 0x3F800000.
16-bit encoding fields
base = x2/sp; fd=00000 -> f0; uimm=4 × 4 = 16 bytes (assembly offset)
15..13
funct3
011
12
uimm[5]
0
11..7
fd
00000
6..4
uimm[4:2]
100
3..2
uimm[7:6]
00
1..0
op
10
Execution data path
x2/sp = 0x00001000; memory 32-bit pattern = 0x3F800000.
0x00001010 = (0x00001000 + 16) mod 2^32
f0 <- 0x3F800000
Architectural state has not been committed.
Quick Understanding & Search Notes
RV32FC: add an unsigned byte offset (0–252, multiples of 4) to x2/sp. On completion, load 32 memory bits into fd.
C.FLWSP is a real 16-bit CI encoding with FLW semantics.
The 5-bit fd field selects f0–f31; f0 is not integer zero. The base is fixed x2/sp.
Assembly offset is 0–252 bytes in multiples of 4; reconstruction implies 2 zero low bits. Do not rescale the assembly value.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — C 2.0The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — F 2.2 / D 2.2The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Zc 1.0The RISC-V Instruction Set Manual, Volume II: Privileged Architecture — Extension Context Status
Common Usage Scenarios
Floating-Point Memory Access
RV32FC, FLEN=32, floating-point state enabled, sp=0x1000, mem32[0x1010]=0x7f800001, access completes: c.flwsp f0, 16(sp) writes the raw pattern into f0 and leaves sp unchanged. With FLEN=64, upper 32 bits are ones.
Pre-Use Checklist
Syntax Check
- The 5-bit fd field selects f0–f31; the base is fixed x2/sp. f0 is not integer zero.
- offset is already an unsigned byte offset: 0–252, in multiples of 4, with 2 implied zero low bits. Do not scale it again.
Semantic Check
- RV32FC, floating-point state enabled, access permitted; load 32 raw bits, with upper bits set to ones when FLEN is wider.
- Address is base plus offset, wrapping at XLEN. Natural alignment raises no address-misaligned exception; misaligned outcomes are EEI-defined and an exception is not shown as a completed access.
Pitfalls / Common Confusions
C.FLWSP is RV32FC-only; RV64C uses the same encoding space for C.LDSP.
Assembly offset is already 0–252 bytes in multiples of 4; do not scale it again.
Natural alignment raises no address-misaligned exception; the EEI defines whether misaligned accesses complete or raise an exception.
With FLEN greater than 32, the load also writes ones to the upper destination bits, creating a valid NaN box.
FAQ
When is c.flwsp available?
This page uses RV32FC, with floating-point state enabled and memory access permitted. C+F implies Zcf on RV32; Zcf depends on Zca and F.