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C.FLWSP

RISC-V C.FLWSP Instruction Details

Instruction ManualCI-format

Load SP FP from sp+offset. CI format, RV32FC.

Instruction Syntax

c.flwsp fd, offset(sp)
Operand Breakdown
This is a CI-format-format instruction. Confirm operand positions based on the assembly syntax.
CFCompressed Instruction
Related Search Terms
c.flwsp instructionc.flwsp syntaxc.flwsp offsetRV32FC c.flwspc.flwsp stack load

Instruction Behavior

c.flwsp in RV32FC, loads a 32-bit single-precision value from sp plus a zero-extended offset scaled by 4 into floating-point fd.

C.FLWSP Decode & Execute Animation

Shows only manual-defined 16-bit fields, operands, and ISA-visible results; it does not model a pipeline, cache, timing, or an implementation's memory-fault handling.

c.flwsp,(sp)
Execution context

This load teaching environment fixes FLEN=32. With a wider FLEN, the 32-bit transfer writes ones to the upper f-register bits, creating a valid NaN-boxed value.

Naturally aligned accesses do not raise an address-misaligned exception; whether a misaligned access completes or raises an address-misaligned/access-fault exception is EEI-defined. This control displays only the selected outcome branch.

x2/sp = 0x00001000; memory 32-bit pattern = 0x3F800000. -> 0x00001010 -> f0 = 0x3F800000.
16-bit encoding fields
15..13
funct3
011
12
uimm[5]
0
11..7
fd
00000
6..4
uimm[4:2]
100
3..2
uimm[7:6]
00
1..0
op
10
Execution data path
x2/sp = 0x00001000; memory 32-bit pattern = 0x3F800000.
0x00001010 = 0x00001000 + 16
f0 <- 0x3F800000
Architectural state has not been committed.

Quick Understanding & Search Notes

c.flwsp in RV32FC, loads a 32-bit single-precision value from sp plus a zero-extended offset scaled by 4 into floating-point fd.

This is a real 16-bit C-extension memory encoding with semantics corresponding to the FLD/FLW/FSD/FSW floating-point load/store family.
C.FLWSP is defined only for RV32FC; RV64C uses the same encoding space for C.LDSP.
The offset is zero-extended and scaled by access width in the encoding; it is not an arbitrary byte immediate.
RISC-V Unprivileged ISA Manual, C compressed extension

Common Usage Scenarios

Register Operations

Understand this scenario with real code like «c.flwsp f0, 16(sp) # f0 = *(sp+16)».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is CI-format.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

C.FLWSP is defined only for RV32FC; RV64C uses the same encoding space for C.LDSP.
The offset is zero-extended and scaled by access width in the encoding; it is not an arbitrary byte immediate.

FAQ

What is the offset unit for c.flwsp?

The encoded immediate is scaled by access width: 8 bytes for double-precision and 4 bytes for single-precision.

Does c.flwsp require a floating-point extension?

Yes. Double-precision forms require D, single-precision forms require F, and all require C.