What is the offset unit for c.flwsp?
The encoded immediate is scaled by access width: 8 bytes for double-precision and 4 bytes for single-precision.
C.FLWSP
RISC-V C.FLWSP Instruction Details
Instruction ManualC-typeLoad SP FP from sp+offset. CI format, RV32FC.
Instruction Syntax
c.flwsp fd, offset(sp)
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CFCompressed Instruction
Related Search Terms
Instruction Behavior
c.flwsp in RV32FC, loads a 32-bit single-precision value from sp plus a zero-extended offset scaled by 4 into floating-point fd.
Quick Understanding & Search Notes
c.flwsp in RV32FC, loads a 32-bit single-precision value from sp plus a zero-extended offset scaled by 4 into floating-point fd.
This is a real 16-bit C-extension memory encoding with semantics corresponding to the FLD/FLW/FSD/FSW floating-point load/store family.
C.FLWSP is defined only for RV32C; RV64C uses the same encoding space for C.LDSP.
The offset is zero-extended and scaled by access width in the encoding; it is not an arbitrary byte immediate.
Common Usage Scenarios
Register Operations
Understand this scenario with real code like «c.flwsp f0, 16(sp) # f0 = *(sp+16)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is C-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
C.FLWSP is defined only for RV32C; RV64C uses the same encoding space for C.LDSP.
The offset is zero-extended and scaled by access width in the encoding; it is not an arbitrary byte immediate.
FAQ
Does c.flwsp require a floating-point extension?
Yes. Double-precision forms require D, single-precision forms require F, and all require C.