Is rs1 in FLW an FP register?
No. rs1 is an integer register that provides the memory base address; rd is the FP destination register.
FLW
RISC-V FLW Instruction Details
Instruction ManualI-typeLoad a 32-bit single-precision floating-point value from memory into an f register.
Instruction Syntax
flw rd, offset(rs1)
Operand Breakdown
RV32/RV64 F; 32-bit I-type LOAD-FP, opcode=0000111 and funct3=010.
rd selects f0–f31, rs1 selects integer x0–x31, and offset is a signed byte displacement in -2048..2047. f0 accepts writes and x0 supplies a zero base.
The address is x[rs1] plus the sign-extended offset, wrapped to XLEN; a successful load copies 32 bits and preserves NaN payloads. Upper bits in wider FLEN are set to ones for NaN-boxing.
Natural alignment is 4 bytes; naturally aligned access has the atomicity guarantee; the EEI determines misaligned completion or exceptions.
FFloating-Point Load
Instruction Behavior
FLW uses the I-type LOAD-FP encoding to load a 32-bit single-precision floating-point bit pattern from the effective address x[rs1] plus a signed 12-bit byte offset into floating-point register f[rd]. The transfer does not modify the bit pattern or canonicalize NaN payloads; when FLEN is greater than 32, the single-precision value is stored using NaN-boxing. Atomicity of naturally aligned access follows the official F-extension rule, while misaligned access is constrained by the execution environment.
FLW Decode And Execute Animation
Shows the F-extension FP load flow: decode the I-type encoding, form the address from an integer base plus a 12-bit offset, and transfer a 32-bit FP bit pattern.
rd
offset
rs1
flw
,
,
Execution Context
fmt=S / width=32
base register is an integer x register
fflags unchanged
31..20
19..15
14..12
11..7
6..0
000000001100
imm[11:0]
01010
rs1
010
FLW
01010
rd
0000111
LOAD-FP
Execution Data Path
instruction
0x00C52507
opcode
0000111 -> LOAD-FP
funct3
010 -> 32-bit load
offset
000000001100 -> 12
rd/rs1
fa0(f10) / a0(x10)
read
a0(x10) = 0x0000000000001000
address
Awaiting Address
write
Not transferred yet; destination unchanged
Current Step
Fetch: show the 32-bit I-type encoding
The word is split as a I-type instruction; FP memory access is not an OP-FP arithmetic encoding.
encoding: 0x00C52507
syntax : flw fa0(f10), 12(a0(x10))
result : Not transferred yet; destination unchanged
Address And Bit-Pattern Transfer
base
0x0000000000001000
offset
12
address
Awaiting Address
alignment
4-byte aligned
loaded bits
Not transferred yet; destination unchanged
FLW writes a 32-bit single-precision value to an FP register; FLEN>32 involves NaN-boxing. The transfer itself does not modify NaN payloads. This example is naturally aligned and cannot raise address-misaligned.
Assumes the extension is available, FS enabled, FLEN=32, and readable memory with no faults except the selected misalignment outcome. The bit-pattern input is the complete 32-bit loaded value; f0 accepts writes and x0 supplies a zero base. Steps are teaching views.
This animation shows only F-extension FP load/store ISA-visible address calculation and bit-pattern transfer; it does not model caches, buses, trap handlers, FPU pipelines, or microarchitectural timing.
Quick Understanding & Search Notes
FLW is the F-extension single-precision floating-point load. It forms the address from integer register rs1 plus a signed 12-bit byte offset, then loads a 32-bit bit pattern into FP register rd; this transfer is not FP arithmetic and does not use rm rounding.
I-type LOAD-FP: imm[11:0], rs1, funct3=010, rd, opcode=0000111.
Effective address = x[rs1] + sign_extend(offset), with the offset measured in bytes.
FLW/FSW do not modify transferred bits; FLW stores a single-precision value in wider FLEN registers using NaN-boxing.
Common Usage Scenarios
Data Loading
Understand this scenario with real code like «flw f0, 0(x10)».
Pre-Use Checklist
Syntax Check
- RV32/RV64 F; 32-bit I-type LOAD-FP, opcode=0000111 and funct3=010.
- rd selects f0–f31, rs1 selects integer x0–x31, and offset is a signed byte displacement in -2048..2047. f0 accepts writes and x0 supplies a zero base.
Semantic Check
- The address is x[rs1] plus the sign-extended offset, wrapped to XLEN; a successful load copies 32 bits and preserves NaN payloads. Upper bits in wider FLEN are set to ones for NaN-boxing.
- Natural alignment is 4 bytes; naturally aligned access has the atomicity guarantee; the EEI determines misaligned completion or exceptions.
Pitfalls / Common Confusions
rs1 is an integer base register, not an FP register; rd is the FP destination register.
offset is a signed 12-bit byte offset in -2048..2047, not a floating-point element index.
FLW transfers a 32-bit bit pattern and does not canonicalize NaN payloads; with FLEN>32 the written value is NaN-boxed.
Only naturally aligned accesses have the specified atomicity guarantee; misaligned behavior depends on the execution environment.
FAQ
Does FLW round according to rm?
No. FLW is a bit-pattern load, not an FP arithmetic operation; the transfer does not canonicalize NaN payloads.