Is the address register an FP register?
No. The base rs1 is an integer register; only the data source/destination is an FP register.
FLW
RISC-V FLW Instruction Details
Instruction ManualI-typeLoad a 32-bit single-precision floating-point value from memory into an f register.
Instruction Syntax
flw rd, offset(rs1)
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
FFloating-Point Load
Related Search Terms
Instruction Encoding
31..20
imm[11:0]
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
FLW uses opcode 0000111 (0x07), funct3 010. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.
Format: I-type
opcode: 0000111 (0x07)
funct3: 010 (0x2)
Instruction Behavior
FLW loads a single-precision floating-point value from memory into floating-point register rd using base+offset addressing mode. The effective address is the base address in rs1 plus a 12-bit signed byte offset. FLW is only guaranteed to execute atomically if the effective address is naturally aligned. Bits are not modified in the transfer; in particular, non-canonical NaN payloads are preserved.
Quick Understanding & Search Notes
FLW is a floating-point load/store instruction. It forms the effective address from integer register rs1 plus a signed 12-bit offset and transfers the bit pattern between memory and an FP register.
The transfer width is 32 bits; FLW NaN-boxes the value when writing the FP register.
Atomicity of naturally aligned accesses and handling of misalignment are constrained by the spec and execution environment; this is not a synchronization primitive.
Common Usage Scenarios
Data Loading
Understand this scenario with real code like «flw f0, 0(x10)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Misaligned addresses may cause traps or performance degradation
In RV64, FLW NaN-boxes the upper 32 bits of the FP register (all-1s NaN-boxing)
Offset range limited to ±2KB
FAQ
What is the offset range?
The offset is a signed 12-bit immediate, encoding -2048 to 2047 bytes.