Does FSW take the address from an FP register?
No. The address base comes from integer register rs1; FP register rs2 only supplies the data bit pattern to store.
FSW
RISC-V FSW Instruction Details
Instruction ManualS-typeStore a 32-bit single-precision floating-point value from an f register to memory.
Instruction Syntax
fsw rs2, offset(rs1)
Operand Breakdown
RV32/RV64 F 2.2; 32-bit S-type STORE-FP, opcode=0100111 and funct3=010.
rs2 selects FP f0–f31, rs1 selects integer x0–x31, and offset is a signed byte displacement in -2048..2047. x0 supplies zero; f0 is an ordinary FP source.
The address is x[rs1] plus the sign-extended offset, wrapped to XLEN. A successful store transfers the low 32 bits, ignores higher bits without checking NaN-boxing, and preserves NaN payloads; no rounding or fflags update occurs.
Natural alignment is 4 bytes; naturally aligned access has the atomicity guarantee; the EEI determines misaligned completion or exceptions. An exception does not guarantee that all memory remains unchanged.
FFloating-Point Store
Instruction Behavior
FSW uses the S-type STORE-FP encoding to store the 32-bit single-precision floating-point bit pattern from f[rs2] to the effective address x[rs1] plus a signed 12-bit byte offset. The transfer performs no FP rounding and does not modify or canonicalize NaN payloads. Atomicity of naturally aligned access follows the official F-extension rule, while misaligned access is constrained by the execution environment.
FSW Decode And Execute Animation
Shows the F-extension FP store flow: decode the S-type encoding, form the address from an integer base plus a 12-bit offset, and transfer a 32-bit FP bit pattern.
rs2
offset
rs1
fsw
,
,
Execution Context
fmt=S / width=32
base register is an integer x register
fflags unchanged
31..25
24..20
19..15
14..12
11..7
6..0
0000000
imm[11:5]
01011
rs2
01010
rs1
010
FSW
01100
imm[4:0]
0100111
STORE-FP
Execution Data Path
instruction
0x00B52627
opcode
0100111 -> STORE-FP
funct3
010 -> 32-bit store
offset
000000001100 -> 12
rs2/rs1
fa1(f11) / a0(x10)
read
a0(x10) = 0x0000000000001000, fa1(f11) = 0x40490FDB
address
Awaiting Address
memory
Not stored yet; memory not updated
Current Step
Fetch: show the 32-bit S-type encoding
The word is split as a S-type instruction; FP memory access is not an OP-FP arithmetic encoding.
encoding: 0x00B52627
syntax : fsw fa1(f11), 12(a0(x10))
result : Not stored yet; memory not updated
Address And Bit-Pattern Transfer
base
0x0000000000001000
offset
12
address
Awaiting Address
alignment
4-byte aligned
stored bits
Not stored yet; memory not updated
FSW stores a 32-bit single-precision bit pattern, does not write an FP register, and performs no rounding or NaN canonicalization.
Assumes the extension and FS are enabled and the address is accessible. Shows the selected EEI branch without modeling protection or translation. The source input supplies the low bits; stores ignore higher bits without checking NaN-boxing. Steps are teaching views.
This animation shows only F-extension FP load/store ISA-visible address calculation and bit-pattern transfer; it does not model caches, buses, trap handlers, FPU pipelines, or microarchitectural timing.
Quick Understanding & Search Notes
FSW is the F-extension single-precision floating-point store. It computes the address from an integer base and a 12-bit byte offset, then writes the 32-bit single-precision bit pattern from f[rs2] to memory; it is not an FP operation and has no rm rounding step.
S-type STORE-FP: imm[11:5], rs2, rs1, funct3=010, imm[4:0], opcode=0100111.
Effective address = x[rs1] + sign_extend(offset), with the offset measured in bytes.
FSW stores the single-precision bit pattern from the source FP register without canonicalizing NaN payloads.
Common Usage Scenarios
Data Storing
Understand this scenario with real code like «fsw f0, 0(x10)».
Pre-Use Checklist
Syntax Check
- RV32/RV64 F 2.2; 32-bit S-type STORE-FP, opcode=0100111 and funct3=010.
- rs2 selects FP f0–f31, rs1 selects integer x0–x31, and offset is a signed byte displacement in -2048..2047. x0 supplies zero; f0 is an ordinary FP source.
Semantic Check
- The address is x[rs1] plus the sign-extended offset, wrapped to XLEN. A successful store transfers the low 32 bits, ignores higher bits without checking NaN-boxing, and preserves NaN payloads; no rounding or fflags update occurs.
- Natural alignment is 4 bytes; naturally aligned access has the atomicity guarantee; the EEI determines misaligned completion or exceptions. An exception does not guarantee that all memory remains unchanged.
Pitfalls / Common Confusions
rs1 is an integer base register; rs2 is the FP source register.
offset is a signed 12-bit byte offset in -2048..2047.
FSW stores a 32-bit bit pattern and performs no FP rounding or NaN canonicalization.
FSW does not write an FP register; load-time NaN-boxing is not a store-stage writeback action.
FAQ
Does FSW change fflags?
No. FSW is a bit-pattern store and performs no FP arithmetic or rounding; by ISA-visible semantics it does not set floating-point exception flags, and the animation shows fflags unchanged.