RVOPcode
Home/Instructions/Store Float Word
FSW

RISC-V FSW Instruction Details

Instruction ManualS-type

Store a 32-bit single-precision floating-point value from an f register to memory.

Instruction Syntax

fsw rs2, offset(rs1)
Operand Breakdown
Source rs2: register holding data to write to memory.
Base rs1: register holding the base address.
Immediate offset: 12-bit signed value added to rs1 for the final address.
FFloating-Point Store
Related Search Terms
FSW instructionRISC-V FSWfsw syntaxfsw encodingfsw Fsingle-precision FP store

Instruction Encoding

31..25
imm[11:5]
24..20
rs2
19..15
rs1
14..12
funct3
11..7
imm[4:0]
6..0
opcode

FSW uses opcode 0100111 (0x27), funct3 010. The rs1 field holds the base address, rs2 holds the store data, and the 12-bit immediate split across imm[11:5] and imm[4:0] provides the offset.

Format: S-type
opcode: 0100111 (0x27)
funct3: 010 (0x2)

Instruction Behavior

FSW stores a single-precision floating-point value from floating-point register rs2 to memory using base+offset addressing mode. The effective address is the base address in rs1 plus a 12-bit signed byte offset. FSW is only guaranteed to execute atomically if the effective address is naturally aligned. Bits are not modified in the transfer.

Quick Understanding & Search Notes

FSW is a single-precision floating-point store. It forms the address from an integer base plus a signed 12-bit offset and writes the 32-bit single-precision bit pattern from f[rs2] to memory.

FSW stores the low 32-bit single-precision bit pattern from floating-point register f[rs2] to memory.
FLW/FSW transfer bit patterns without canonicalizing NaN payloads; FSW does not write an FP register and has no load-time NaN-boxing step.
RISC-V Unprivileged ISA Manual, F Extension

Common Usage Scenarios

Data Storing

Understand this scenario with real code like «fsw f0, 0(x10)».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is S-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Misaligned addresses may cause traps or performance degradation
Only stores low 32 bits of FP register; NaN-box upper bits ignored in RV64
Offset range limited to ±2KB

FAQ

Is the address register an FP register?

No. The base rs1 is an integer register; only the data source/destination is an FP register.

What is the offset range?

The offset is a signed 12-bit immediate, encoding -2048 to 2047 bytes.