Does FSW take the address from an FP register?
No. The address base comes from integer register rs1; FP register rs2 only supplies the data bit pattern to store.
FSW
RISC-V FSW Instruction Details
Instruction ManualS-typeStore a 32-bit single-precision floating-point value from an f register to memory.
Instruction Syntax
fsw rs2, offset(rs1)
Operand Breakdown
Source rs2: register holding data to write to memory.
Base rs1: register holding the base address.
Immediate offset: 12-bit signed value added to rs1 for the final address.
FFloating-Point Store
Instruction Behavior
FSW uses the S-type STORE-FP encoding to store the 32-bit single-precision floating-point bit pattern from f[rs2] to the effective address x[rs1] plus a signed 12-bit byte offset. The transfer performs no FP rounding and does not modify or canonicalize NaN payloads. Atomicity of naturally aligned access follows the official F-extension rule, while misaligned access is constrained by the execution environment.
FSW Decode And Execute Animation
Shows the F-extension FP store flow: decode the S-type encoding, form the address from an integer base plus a 12-bit offset, and transfer a 32-bit FP bit pattern.
rs2
offset
rs1
fsw
,
,
Execution Context
fmt=S / width=32
base register is an integer x register
fflags unchanged
31..25
24..20
19..15
14..12
11..7
6..0
0000000
imm[11:5]
01011
rs2
01010
rs1
010
FSW
01100
imm[4:0]
0100111
STORE-FP
Execution Data Path
instruction
0x00B52627
opcode
0100111 -> STORE-FP
funct3
010 -> 32-bit store
offset
000000001100 -> 12
rs2/rs1
fa1(f11) / a0(x10)
read
a0(x10) = 0x0000000000001000, fa1(f11) = 0x40490FDB
address
0x0000000000001000 + (12) = 0x000000000000100C
memory
memory[0x000000000000100C] = 0x40490FDB
Current Step
Fetch: show the 32-bit S-type encoding
The word is split as a S-type instruction; FP memory access is not an OP-FP arithmetic encoding.
encoding: 0x00B52627
syntax : fsw fa1(f11), 12(a0(x10))
result : memory[0x000000000000100C] = 0x40490FDB
Address And Bit-Pattern Transfer
base
0x0000000000001000
offset
12
address
0x000000000000100C
stored bits
0x40490FDB
FSW stores a 32-bit single-precision bit pattern, does not write an FP register, and performs no rounding or NaN canonicalization.
This animation shows only F-extension FP load/store ISA-visible address calculation and bit-pattern transfer; it does not model caches, buses, trap handlers, FPU pipelines, or microarchitectural timing.
Quick Understanding & Search Notes
FSW is the F-extension single-precision floating-point store. It computes the address from an integer base and a 12-bit byte offset, then writes the 32-bit single-precision bit pattern from f[rs2] to memory; it is not an FP operation and has no rm rounding step.
S-type STORE-FP: imm[11:5], rs2, rs1, funct3=010, imm[4:0], opcode=0100111.
Effective address = x[rs1] + sign_extend(offset), with the offset measured in bytes.
FSW stores the single-precision bit pattern from the source FP register without canonicalizing NaN payloads.
Common Usage Scenarios
Data Storing
Understand this scenario with real code like «fsw f0, 0(x10)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is S-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
rs1 is an integer base register; rs2 is the FP source register.
offset is a signed 12-bit byte offset in -2048..2047.
FSW stores a 32-bit bit pattern and performs no FP rounding or NaN canonicalization.
FSW does not write an FP register; load-time NaN-boxing is not a store-stage writeback action.
FAQ
Does FSW change fflags?
No. FSW is a bit-pattern store and performs no FP arithmetic or rounding; by ISA-visible semantics it does not set floating-point exception flags, and the animation shows fflags unchanged.