Is the address register an FP register?
No. The base rs1 is an integer register; only the data source/destination is an FP register.
FSD
RISC-V FSD Instruction Details
Instruction ManualS-typeStore 64-bit double-precision FP from f register to memory.
Instruction Syntax
fsd rs2, offset(rs1)
Operand Breakdown
Source rs2: register holding data to write to memory.
Base rs1: register holding the base address.
Immediate offset: 12-bit signed value added to rs1 for the final address.
DFloating-Point Store
Related Search Terms
Instruction Encoding
31..25
imm[11:5]
24..20
rs2
19..15
rs1
14..12
funct3
11..7
imm[4:0]
6..0
opcode
FSD uses opcode 0100111 (0x27), funct3 011. The rs1 field holds the base address, rs2 holds the store data, and the 12-bit immediate split across imm[11:5] and imm[4:0] provides the offset.
Format: S-type
opcode: 0100111 (0x27)
funct3: 011 (0x3)
Instruction Behavior
FSD stores a 64-bit double-precision FP value from f[rs2] to memory using base+offset addressing (S-type format). May be a NaN-boxed value. Only guaranteed atomic when naturally aligned and XLEN≥64. Bits transferred unmodified.
Quick Understanding & Search Notes
FSD is a floating-point load/store instruction. It forms the effective address from integer register rs1 plus a signed 12-bit offset and transfers the bit pattern between memory and an FP register.
The transfer width is 64 bits; D-extension double transfers do not interpret or canonicalize NaN payloads.
Atomicity of naturally aligned accesses and handling of misalignment are constrained by the spec and execution environment; this is not a synchronization primitive.
Common Usage Scenarios
Data Storing
Understand this scenario with real code like «fsd f0, 0(x10)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is S-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
misaligned may not be atomic on XLEN<64
FAQ
What is the offset range?
The offset is a signed 12-bit immediate, encoding -2048 to 2047 bytes.