Does FSD convert the floating-point data?
No. FSD writes the 64-bit bit pattern from the source FP register to memory without rounding or format conversion.
FSD
RISC-V FSD Instruction Details
Instruction ManualS-typeStore 64-bit double-precision FP from f register to memory.
Instruction Syntax
fsd rs2, offset(rs1)
Operand Breakdown
Source rs2: register holding data to write to memory.
Base rs1: register holding the base address.
Immediate offset: 12-bit signed value added to rs1 for the final address.
DFloating-Point Store
Instruction Behavior
FSD uses the S-type STORE-FP encoding to store the 64-bit double-precision floating-point bit pattern from f[rs2] to the effective address x[rs1] plus a signed 12-bit byte offset. The transfer performs no FP rounding and does not modify or canonicalize NaN payloads. FSD access atomicity is guaranteed by the official D-extension rule only when the effective address is naturally aligned and XLEN is at least 64; misaligned access is constrained by the execution environment.
FSD Decode And Execute Animation
Shows the D-extension FP store flow: decode the S-type encoding, form the address from an integer base plus a 12-bit offset, and transfer a 64-bit FP bit pattern.
rs2
offset
rs1
fsd
,
,
Execution Context
fmt=D / width=64
base register is an integer x register
fflags unchanged
31..25
24..20
19..15
14..12
11..7
6..0
0000000
imm[11:5]
01011
rs2
01010
rs1
011
FSD
10000
imm[4:0]
0100111
STORE-FP
Execution Data Path
instruction
0x00B53827
opcode
0100111 -> STORE-FP
funct3
011 -> 64-bit store
offset
000000010000 -> 16
rs2/rs1
fa1(f11) / a0(x10)
read
a0(x10) = 0x0000000000001000, fa1(f11) = 0x400921FB54442D18
address
0x0000000000001000 + (16) = 0x0000000000001010
memory
memory[0x0000000000001010] = 0x400921FB54442D18
Current Step
Fetch: show the 32-bit S-type encoding
The word is split as a S-type instruction; FP memory access is not an OP-FP arithmetic encoding.
encoding: 0x00B53827
syntax : fsd fa1(f11), 16(a0(x10))
result : memory[0x0000000000001010] = 0x400921FB54442D18
Address And Bit-Pattern Transfer
base
0x0000000000001000
offset
16
address
0x0000000000001010
stored bits
0x400921FB54442D18
FSD transfers a 64-bit double-precision bit pattern; atomicity of naturally aligned access and misaligned handling follow the official spec and execution environment.
This animation shows only D-extension FP load/store ISA-visible address calculation and bit-pattern transfer; it does not model caches, buses, trap handlers, FPU pipelines, or microarchitectural timing.
Quick Understanding & Search Notes
FSD is the D-extension double-precision floating-point store. It computes the address from an integer base and a 12-bit byte offset, then writes the 64-bit double-precision bit pattern from f[rs2] to memory; it is not FP arithmetic and has no rm rounding step.
S-type STORE-FP: imm[11:5], rs2, rs1, funct3=011, imm[4:0], opcode=0100111.
Effective address = x[rs1] + sign_extend(offset), with the offset measured in bytes.
FSD transfers a 64-bit bit pattern; naturally aligned access is atomic when XLEN>=64.
Common Usage Scenarios
Data Storing
Understand this scenario with real code like «fsd f0, 0(x10)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is S-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
rs1 is an integer base register; rs2 is the FP source register.
offset is a signed 12-bit byte offset in -2048..2047.
FSD stores a 64-bit double-precision bit pattern and performs no FP rounding or NaN canonicalization.
The atomicity guarantee requires natural alignment and XLEN>=64; misaligned handling is determined by the execution environment.
FAQ
Is the FSD address register an FP register?
No. rs1 is an integer register; rs2 is the FP register that supplies the data.