What is the offset unit for c.fld?
The encoded immediate is scaled by access width: 8 bytes for double-precision and 4 bytes for single-precision.
C.FLD
RISC-V C.FLD Instruction Details
Instruction ManualCL-formatLoad double FP from memory into fd'. CL format, requires D extension.
Instruction Syntax
c.fld fd', offset(rs1')
Operand Breakdown
This is a CL-format-format instruction. Confirm operand positions based on the assembly syntax.
CDCompressed Instruction
Related Search Terms
Instruction Behavior
c.fld loads a 64-bit double-precision value from rs1' plus a zero-extended offset scaled by 8 into fd'.
C.FLD Decode & Execute Animation
Shows only manual-defined 16-bit fields, operands, and ISA-visible results; it does not model a pipeline, cache, timing, or an implementation's memory-fault handling.
c.fld,(rs1')
Execution context
This load teaching environment fixes FLEN=64. With a wider FLEN, the 64-bit transfer writes ones to the upper f-register bits, creating a valid NaN-boxed value.
Naturally aligned accesses do not raise an address-misaligned exception; whether a misaligned access completes or raises an address-misaligned/access-fault exception is EEI-defined. This control displays only the selected outcome branch.
x10 = 0x0000000000001000; memory 64-bit pattern = 0x3FF0000000000000. -> 0x0000000000001010 -> f8 = 0x3FF0000000000000.
16-bit encoding fields
15..13
funct3
101
12..10
uimm[5:3]
010
9..7
rs1'
010
6..5
uimm[7:6]
00
4..2
fd'
000
1..0
op
00
Execution data path
x10 = 0x0000000000001000; memory 64-bit pattern = 0x3FF0000000000000.
0x0000000000001010 = 0x0000000000001000 + 16
f8 <- 0x3FF0000000000000
Architectural state has not been committed.
Quick Understanding & Search Notes
c.fld loads a 64-bit double-precision value from rs1' plus a zero-extended offset scaled by 8 into fd'.
This is a real 16-bit C-extension memory encoding with semantics corresponding to the FLD/FLW/FSD/FSW floating-point load/store family.
Available in RV32DC/RV64DC; fd' and rs1' use the f8..f15/x8..x15 compressed register subsets.
The offset is zero-extended and scaled by access width in the encoding; it is not an arbitrary byte immediate.
Common Usage Scenarios
Floating-Point Memory Access
Understand this scenario with real code like «c.fld f8, 0(x10)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is CL-format.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Available in RV32DC/RV64DC; fd' and rs1' use the f8..f15/x8..x15 compressed register subsets.
The offset is zero-extended and scaled by access width in the encoding; it is not an arbitrary byte immediate.
Naturally aligned addresses do not raise an address-misaligned exception; the execution environment defines whether a misaligned access completes or raises an exception.
When FLEN is greater than 64, the narrower FLD transfer writes ones to the destination floating-point register's upper bits, creating a valid NaN-boxed double-precision value.
FAQ
Does c.fld require a floating-point extension?
Yes. Double-precision forms require D, single-precision forms require F, and all require C.