How is the offset written for c.fld?
Use a byte offset from 0 through 248, in multiples of 8. For example, offset=16 adds 16 bytes to the address.
C.FLD
RISC-V C.FLD Instruction Details
Instruction ManualCL-formatRV32DC/RV64DC compressed 64-bit floating-point load; base=x8–x15, destination=f8–f15.
Instruction Syntax
c.fld fd', offset(rs1')
The 3-bit fd′ field selects f8–f15; the 3-bit rs1′ field selects x8–x15 in a separate register file.
offset is already an unsigned byte offset: 0–248, in multiples of 8; the encoding implies 3 zero low bits.
RV32DC/RV64DC, with floating-point state enabled; a completed access loads 64 raw bits and sets upper bits to ones when FLEN is wider.
The effective address is base plus offset. Natural alignment raises no address-misaligned exception; misaligned outcomes are EEI-defined, and faults do not commit ordinary floating-point destination writeback.
CDCompressed Instruction
Related Search Terms
Instruction Behavior
A 16-bit RV32DC/RV64DC CL load: add an unsigned byte offset (0–248, multiples of 8) to x[rs1']; on completion, load the 64-bit memory pattern into fd'.
C.FLD Decode & Execute Animation
Shows only manual-defined 16-bit fields, operands, and ISA-visible results; it does not model a pipeline, cache, timing, or an implementation's memory-fault handling.
c.fld,(rs1')
Execution context
RV32DC/RV64DC; floating-point state enabled, ordinary address calculation (no address-transforming extensions), and memory bits already assembled using the environment's byte order.
This load teaching environment fixes FLEN=64. With a wider FLEN, the 64-bit transfer writes ones to the upper f-register bits, creating a valid NaN-boxed value.
Naturally aligned accesses do not raise an address-misaligned exception; whether a misaligned access completes or raises an address-misaligned/access-fault exception is EEI-defined. This control displays only the selected outcome branch.
x10 = 0x0000000000001000; memory 64-bit pattern = 0x3FF0000000000000. -> 0x0000000000001010 -> f8 = 0x3FF0000000000000.
16-bit encoding fields
rs1'=010 -> x10; fd'=000 -> f8; uimm=2 × 8 = 16 bytes (assembly offset)
15..13
funct3
001
12..10
uimm[5:3]
010
9..7
rs1'
010
6..5
uimm[7:6]
00
4..2
fd'
000
1..0
op
00
Execution data path
x10 = 0x0000000000001000; memory 64-bit pattern = 0x3FF0000000000000.
0x0000000000001010 = (0x0000000000001000 + 16) mod 2^64
f8 <- 0x3FF0000000000000
Architectural state has not been committed.
Quick Understanding & Search Notes
A 16-bit RV32DC/RV64DC CL load: add an unsigned byte offset (0–248, multiples of 8) to x[rs1']; on completion, load the 64-bit memory pattern into fd'.
C.FLD has a real 16-bit CL encoding with FLD semantics.
This page uses RV32DC/RV64DC; the 3-bit rs1′ field maps to x8–x15 and the 3-bit fd′ field maps to f8–f15.
Assembly offset is already a byte offset: 0–248, in multiples of 8. The encoding implies 3 zero low bits; do not multiply the assembly value by 8 again.
Common Usage Scenarios
Floating-Point Memory Access
RV64DC, FLEN=64, floating-point state enabled, x10=0x1000, assembled memory bits=0x7ff0000000000001, access completes: c.fld f8, 0(x10) writes those bits unchanged to f8 without floating-point arithmetic.
Pre-Use Checklist
Syntax Check
- The 3-bit fd′ field selects f8–f15; the 3-bit rs1′ field selects x8–x15 in a separate register file.
- offset is already an unsigned byte offset: 0–248, in multiples of 8; the encoding implies 3 zero low bits.
Semantic Check
- RV32DC/RV64DC, with floating-point state enabled; a completed access loads 64 raw bits and sets upper bits to ones when FLEN is wider.
- The effective address is base plus offset. Natural alignment raises no address-misaligned exception; misaligned outcomes are EEI-defined, and faults do not commit ordinary floating-point destination writeback.
Pitfalls / Common Confusions
Available in RV32DC/RV64DC; fd' and rs1' use the f8..f15/x8..x15 compressed register subsets.
Assembly offset is 0–248 bytes in multiples of 8; do not scale it again.
Naturally aligned addresses do not raise an address-misaligned exception; the execution environment defines whether a misaligned access completes or raises an exception.
When FLEN is greater than 64, the narrower FLD transfer writes ones to the destination floating-point register's upper bits, creating a valid NaN-boxed double-precision value.
FAQ
When is c.fld available?
This page uses RV32DC/RV64DC. Floating-point state must also be enabled and memory access permitted; an access exception does not commit an ordinary floating-point destination writeback.