What is the offset unit for c.fldsp?
The encoded immediate is scaled by access width: 8 bytes for double-precision and 4 bytes for single-precision.
C.FLDSP
RISC-V C.FLDSP Instruction Details
Instruction ManualCI-formatLoad double FP from sp+offset. CI format, RV32DC/RV64DC.
Instruction Syntax
c.fldsp fd, offset(sp)
Operand Breakdown
This is a CI-format-format instruction. Confirm operand positions based on the assembly syntax.
CDCompressed Instruction
Instruction Behavior
c.fldsp loads a 64-bit double-precision value from sp plus a zero-extended offset scaled by 8 into floating-point fd.
C.FLDSP Decode & Execute Animation
Shows only manual-defined 16-bit fields, operands, and ISA-visible results; it does not model a pipeline, cache, timing, or an implementation's memory-fault handling.
c.fldsp,(sp)
Execution context
This load teaching environment fixes FLEN=64. With a wider FLEN, the 64-bit transfer writes ones to the upper f-register bits, creating a valid NaN-boxed value.
Naturally aligned accesses do not raise an address-misaligned exception; whether a misaligned access completes or raises an address-misaligned/access-fault exception is EEI-defined. This control displays only the selected outcome branch.
x2/sp = 0x0000000000001000; memory 64-bit pattern = 0x3FF0000000000000. -> 0x0000000000001010 -> f0 = 0x3FF0000000000000.
16-bit encoding fields
15..13
funct3
001
12
uimm[5]
0
11..7
fd
00000
6..5
uimm[4:3]
10
4..2
uimm[8:6]
000
1..0
op
10
Execution data path
x2/sp = 0x0000000000001000; memory 64-bit pattern = 0x3FF0000000000000.
0x0000000000001010 = 0x0000000000001000 + 16
f0 <- 0x3FF0000000000000
Architectural state has not been committed.
Quick Understanding & Search Notes
c.fldsp loads a 64-bit double-precision value from sp plus a zero-extended offset scaled by 8 into floating-point fd.
This is a real 16-bit C-extension memory encoding with semantics corresponding to the FLD/FLW/FSD/FSW floating-point load/store family.
The base is fixed to x2/sp; the destination is a floating-point register; D and C are required.
The offset is zero-extended and scaled by access width in the encoding; it is not an arbitrary byte immediate.
Common Usage Scenarios
Floating-Point Memory Access
Understand this scenario with real code like «c.fldsp f0, 16(sp) # f0 = *(sp+16)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is CI-format.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The base is fixed to x2/sp; the destination is a floating-point register; D and C are required.
The offset is zero-extended and scaled by access width in the encoding; it is not an arbitrary byte immediate.
Naturally aligned addresses do not raise an address-misaligned exception; the execution environment defines whether a misaligned access completes or raises an exception.
When FLEN is greater than 64, the narrower FLD transfer writes ones to the destination floating-point register's upper bits, creating a valid NaN-boxed double-precision value.
FAQ
Does c.fldsp require a floating-point extension?
Yes. Double-precision forms require D, single-precision forms require F, and all require C.