How is the offset written for c.fldsp?
Use a byte offset from 0 through 504, in multiples of 8. For example, offset=16 adds 16 bytes to the address.
C.FLDSP
RISC-V C.FLDSP Instruction Details
Instruction ManualCI-formatRV32DC/RV64DC compressed 64-bit floating-point load; fixed x2/sp base, fd=f0–f31.
Instruction Syntax
c.fldsp fd, offset(sp)
fd selects any f0–f31; f0 is not integer zero register x0. The base is fixed x2/sp.
offset is already an unsigned byte offset: 0–504, in multiples of 8; the encoding implies 3 zero low bits.
RV32DC/RV64DC, with floating-point state enabled; a completed access loads 64 raw bits and sets upper bits to ones when FLEN is wider.
The effective address is base plus offset. Natural alignment raises no address-misaligned exception; misaligned outcomes are EEI-defined, and faults do not commit ordinary floating-point destination writeback.
CDCompressed Instruction
Instruction Behavior
A 16-bit RV32DC/RV64DC CI load: add an unsigned byte offset (0–504, multiples of 8) to x2/sp; on completion, load the 64-bit memory pattern into fd.
C.FLDSP Decode & Execute Animation
Shows only manual-defined 16-bit fields, operands, and ISA-visible results; it does not model a pipeline, cache, timing, or an implementation's memory-fault handling.
c.fldsp,(sp)
Execution context
RV32DC/RV64DC; floating-point state enabled, ordinary address calculation (no address-transforming extensions), and memory bits already assembled using the environment's byte order.
This load teaching environment fixes FLEN=64. With a wider FLEN, the 64-bit transfer writes ones to the upper f-register bits, creating a valid NaN-boxed value.
Naturally aligned accesses do not raise an address-misaligned exception; whether a misaligned access completes or raises an address-misaligned/access-fault exception is EEI-defined. This control displays only the selected outcome branch.
x2/sp = 0x0000000000001000; memory 64-bit pattern = 0x3FF0000000000000. -> 0x0000000000001010 -> f0 = 0x3FF0000000000000.
16-bit encoding fields
base = x2/sp; fd=00000 -> f0; uimm=2 × 8 = 16 bytes (assembly offset)
15..13
funct3
001
12
uimm[5]
0
11..7
fd
00000
6..5
uimm[4:3]
10
4..2
uimm[8:6]
000
1..0
op
10
Execution data path
x2/sp = 0x0000000000001000; memory 64-bit pattern = 0x3FF0000000000000.
0x0000000000001010 = (0x0000000000001000 + 16) mod 2^64
f0 <- 0x3FF0000000000000
Architectural state has not been committed.
Quick Understanding & Search Notes
A 16-bit RV32DC/RV64DC CI load: add an unsigned byte offset (0–504, multiples of 8) to x2/sp; on completion, load the 64-bit memory pattern into fd.
C.FLDSP has a real 16-bit CI encoding with FLD semantics.
This page uses RV32DC/RV64DC; the base is fixed x2/sp and fd may select f0–f31; f0 is not hardwired to zero.
Assembly offset is already a byte offset: 0–504, in multiples of 8. The encoding implies 3 zero low bits; do not multiply the assembly value by 8 again.
Common Usage Scenarios
Floating-Point Memory Access
RV64DC, FLEN=64, floating-point state enabled, sp=0x1000, assembled memory bits at 0x1010=0x3ff0000000000000, access completes: c.fldsp f0, 16(sp) writes those bits to f0 and leaves sp unchanged.
Pre-Use Checklist
Syntax Check
- fd selects any f0–f31; f0 is not integer zero register x0. The base is fixed x2/sp.
- offset is already an unsigned byte offset: 0–504, in multiples of 8; the encoding implies 3 zero low bits.
Semantic Check
- RV32DC/RV64DC, with floating-point state enabled; a completed access loads 64 raw bits and sets upper bits to ones when FLEN is wider.
- The effective address is base plus offset. Natural alignment raises no address-misaligned exception; misaligned outcomes are EEI-defined, and faults do not commit ordinary floating-point destination writeback.
Pitfalls / Common Confusions
The base is fixed to x2/sp; the destination is a floating-point register; D and C are required.
Assembly offset is 0–504 bytes in multiples of 8; do not scale it again.
Naturally aligned addresses do not raise an address-misaligned exception; the execution environment defines whether a misaligned access completes or raises an exception.
When FLEN is greater than 64, the narrower FLD transfer writes ones to the destination floating-point register's upper bits, creating a valid NaN-boxed double-precision value.
FAQ
When is c.fldsp available?
This page uses RV32DC/RV64DC. Floating-point state must also be enabled and memory access permitted; an access exception does not commit an ordinary floating-point destination writeback.