How is the offset written for c.fsdsp?
Use a byte offset from 0 through 504 in multiples of 8. offset=16 adds 16 bytes without modifying the base.
C.FSDSP
RISC-V C.FSDSP Instruction Details
Instruction ManualCSS-formatRV32DC/RV64DC 16-bit CSS floating-point store, transferring 64 bits; base is x2/sp.
Instruction Syntax
c.fsdsp fs2, offset(sp)
The 5-bit fs2 field selects f0–f31; the base is fixed x2/sp. f0 is not integer zero.
offset is already an unsigned byte offset: 0–504, in multiples of 8, with 3 implied zero low bits. Do not scale it again.
RV32DC/RV64DC, floating-point state enabled, access permitted; store the low 64 source bits, preserving NaN payloads and leaving source and base unchanged.
Address is base plus offset, wrapping at XLEN. Natural alignment raises no address-misaligned exception; misaligned outcomes are EEI-defined and an exception is not shown as a completed access.
CDCompressed Instruction
Instruction Behavior
RV32DC/RV64DC: add an unsigned byte offset (0–504, multiples of 8) to x2/sp. On completion, store the low 64 bits of fs2; source and base stay unchanged.
C.FSDSP Decode & Execute Animation
Shows only manual-defined 16-bit fields, operands, and ISA-visible results; it does not model a pipeline, cache, timing, or an implementation's memory-fault handling.
c.fsdsp,(sp)
Execution context
RV32DC/RV64DC; floating-point state enabled, ordinary address calculation (no address-transforming extensions), and memory bits already assembled using the environment's byte order.
The store transfers 64 bits; with a wider FLEN, FSW transfers the low 32 bits and ignores upper bits, while FSD transfers the low 64 bits. Transfers do not modify NaN payloads.
Naturally aligned accesses do not raise an address-misaligned exception; whether a misaligned access completes or raises an address-misaligned/access-fault exception is EEI-defined. This control displays only the selected outcome branch.
x2/sp = 0x0000000000001000; low 64 bits of f0 = 0x3FF0000000000000. -> 0x0000000000001010 -> M[0x0000000000001010] = 0x3FF0000000000000.
16-bit encoding fields
base = x2/sp; fs2=00000 -> f0; uimm=2 × 8 = 16 bytes (assembly offset)
15..13
funct3
101
12..10
uimm[5:3]
010
9..7
uimm[8:6]
000
6..2
fs2
00000
1..0
op
10
Execution data path
x2/sp = 0x0000000000001000; low 64 bits of f0 = 0x3FF0000000000000.
0x0000000000001010 = (0x0000000000001000 + 16) mod 2^64
M[0x0000000000001010] <- 0x3FF0000000000000
Architectural state has not been committed.
Quick Understanding & Search Notes
RV32DC/RV64DC: add an unsigned byte offset (0–504, multiples of 8) to x2/sp. On completion, store the low 64 bits of fs2; source and base stay unchanged.
C.FSDSP is a real 16-bit CSS encoding with FSD semantics.
The 5-bit fs2 field selects f0–f31. The base is fixed x2/sp.
Assembly offset is 0–504 bytes in multiples of 8; reconstruction implies 3 zero low bits. Do not rescale the assembly value.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — C 2.0The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — F 2.2 / D 2.2The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Zc 1.0The RISC-V Instruction Set Manual, Volume II: Privileged Architecture — Extension Context Status
Common Usage Scenarios
Floating-Point Memory Access
RV64DC, floating-point state enabled, sp=0x1000, low 64 bits of f0=0x3ff0000000000000, access completes: c.fsdsp f0, 16(sp) writes this pattern to mem64[0x1010], leaving f0 and sp unchanged.
Pre-Use Checklist
Syntax Check
- The 5-bit fs2 field selects f0–f31; the base is fixed x2/sp. f0 is not integer zero.
- offset is already an unsigned byte offset: 0–504, in multiples of 8, with 3 implied zero low bits. Do not scale it again.
Semantic Check
- RV32DC/RV64DC, floating-point state enabled, access permitted; store the low 64 source bits, preserving NaN payloads and leaving source and base unchanged.
- Address is base plus offset, wrapping at XLEN. Natural alignment raises no address-misaligned exception; misaligned outcomes are EEI-defined and an exception is not shown as a completed access.
Pitfalls / Common Confusions
This page uses RV32DC/RV64DC; D also depends on F.
Assembly offset is already 0–504 bytes in multiples of 8; do not scale it again.
Natural alignment raises no address-misaligned exception; the EEI defines whether misaligned accesses complete or raise an exception.
The transfer preserves NaN payloads; when FLEN exceeds 64, the store ignores upper bits and transfers only the low 64 bits.
FAQ
When is c.fsdsp available?
This page uses RV32DC/RV64DC, with floating-point state enabled and memory access permitted. C+D implies Zcd; Zcd depends on Zca and D, and D also depends on F.