What is the offset unit for c.fsd?
The encoded immediate is scaled by access width: 8 bytes for double-precision and 4 bytes for single-precision.
C.FSD
RISC-V C.FSD Instruction Details
Instruction ManualCS-formatStore double FP to memory. CS format, requires D extension.
Instruction Syntax
c.fsd fs2', offset(rs1')
Operand Breakdown
This is a CS-format-format instruction. Confirm operand positions based on the assembly syntax.
CDCompressed Instruction
Related Search Terms
Instruction Behavior
c.fsd stores the 64-bit double-precision value from fs2' to rs1' plus a zero-extended offset scaled by 8.
C.FSD Decode & Execute Animation
Shows only manual-defined 16-bit fields, operands, and ISA-visible results; it does not model a pipeline, cache, timing, or an implementation's memory-fault handling.
c.fsd,(rs1')
Execution context
The store transfers 64 bits; with a wider FLEN, FSW transfers the low 32 bits and ignores upper bits, while FSD transfers the low 64 bits. Transfers do not modify NaN payloads.
Naturally aligned accesses do not raise an address-misaligned exception; whether a misaligned access completes or raises an address-misaligned/access-fault exception is EEI-defined. This control displays only the selected outcome branch.
x10 = 0x0000000000001000; low 64 bits of f8 = 0x3FF0000000000000. -> 0x0000000000001010 -> M[0x0000000000001010] = 0x3FF0000000000000.
16-bit encoding fields
15..13
funct3
101
12..10
uimm[5:3]
010
9..7
rs1'
010
6..5
uimm[7:6]
00
4..2
fs2'
000
1..0
op
00
Execution data path
x10 = 0x0000000000001000; low 64 bits of f8 = 0x3FF0000000000000.
0x0000000000001010 = 0x0000000000001000 + 16
M[0x0000000000001010] <- 0x3FF0000000000000
Architectural state has not been committed.
Quick Understanding & Search Notes
c.fsd stores the 64-bit double-precision value from fs2' to rs1' plus a zero-extended offset scaled by 8.
This is a real 16-bit C-extension memory encoding with semantics corresponding to the FLD/FLW/FSD/FSW floating-point load/store family.
Available in RV32DC/RV64DC; source and base use compressed register subsets.
The offset is zero-extended and scaled by access width in the encoding; it is not an arbitrary byte immediate.
Common Usage Scenarios
Compressed & Code Size
Understand this scenario with real code like «c.fsd f8, 0(x10)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is CS-format.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Available in RV32DC/RV64DC; source and base use compressed register subsets.
The offset is zero-extended and scaled by access width in the encoding; it is not an arbitrary byte immediate.
FAQ
Does c.fsd require a floating-point extension?
Yes. Double-precision forms require D, single-precision forms require F, and all require C.