What is the offset unit for c.fsd?
The encoded immediate is scaled by access width: 8 bytes for double-precision and 4 bytes for single-precision.
C.FSD
RISC-V C.FSD Instruction Details
Instruction ManualC-typeStore double FP to memory. CS format, requires D extension.
Instruction Syntax
c.fsd fs2', offset(rs1')
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CDCompressed Instruction
Related Search Terms
Instruction Behavior
c.fsd stores the 64-bit double-precision value from fs2' to rs1' plus a zero-extended offset scaled by 8.
Quick Understanding & Search Notes
c.fsd stores the 64-bit double-precision value from fs2' to rs1' plus a zero-extended offset scaled by 8.
This is a real 16-bit C-extension memory encoding with semantics corresponding to the FLD/FLW/FSD/FSW floating-point load/store family.
Available in RV32DC/RV64DC; source and base use compressed register subsets.
The offset is zero-extended and scaled by access width in the encoding; it is not an arbitrary byte immediate.
Common Usage Scenarios
Compressed & Code Size
Understand this scenario with real code like «c.fsd f8, 0(x10)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is C-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Available in RV32DC/RV64DC; source and base use compressed register subsets.
The offset is zero-extended and scaled by access width in the encoding; it is not an arbitrary byte immediate.
FAQ
Does c.fsd require a floating-point extension?
Yes. Double-precision forms require D, single-precision forms require F, and all require C.