How is the offset written for c.fsd?
Use a byte offset from 0 through 248 in multiples of 8. offset=16 adds 16 bytes without modifying the base.
C.FSD
RISC-V C.FSD Instruction Details
Instruction ManualCS-formatRV32DC/RV64DC 16-bit CS floating-point store, transferring 64 bits; base=x8–x15, source=f8–f15.
Instruction Syntax
c.fsd fs2', offset(rs1')
The 3-bit fs2′ field maps to f8–f15; the 3-bit rs1′ field maps to x8–x15 in the separate integer register file.
offset is already an unsigned byte offset: 0–248, in multiples of 8, with 3 implied zero low bits. Do not scale it again.
RV32DC/RV64DC, floating-point state enabled, access permitted; store the low 64 source bits, preserving NaN payloads and leaving source and base unchanged.
Address is base plus offset, wrapping at XLEN. Natural alignment raises no address-misaligned exception; misaligned outcomes are EEI-defined and an exception is not shown as a completed access.
CDCompressed Instruction
Related Search Terms
Instruction Behavior
RV32DC/RV64DC: add an unsigned byte offset (0–248, multiples of 8) to x[rs1']. On completion, store the low 64 bits of fs2'; source and base stay unchanged.
C.FSD Decode & Execute Animation
Shows only manual-defined 16-bit fields, operands, and ISA-visible results; it does not model a pipeline, cache, timing, or an implementation's memory-fault handling.
c.fsd,(rs1')
Execution context
RV32DC/RV64DC; floating-point state enabled, ordinary address calculation (no address-transforming extensions), and memory bits already assembled using the environment's byte order.
The store transfers 64 bits; with a wider FLEN, FSW transfers the low 32 bits and ignores upper bits, while FSD transfers the low 64 bits. Transfers do not modify NaN payloads.
Naturally aligned accesses do not raise an address-misaligned exception; whether a misaligned access completes or raises an address-misaligned/access-fault exception is EEI-defined. This control displays only the selected outcome branch.
x10 = 0x0000000000001000; low 64 bits of f8 = 0x3FF0000000000000. -> 0x0000000000001010 -> M[0x0000000000001010] = 0x3FF0000000000000.
16-bit encoding fields
rs1'=010 -> x10; fs2'=000 -> f8; uimm=2 × 8 = 16 bytes (assembly offset)
15..13
funct3
101
12..10
uimm[5:3]
010
9..7
rs1'
010
6..5
uimm[7:6]
00
4..2
fs2'
000
1..0
op
00
Execution data path
x10 = 0x0000000000001000; low 64 bits of f8 = 0x3FF0000000000000.
0x0000000000001010 = (0x0000000000001000 + 16) mod 2^64
M[0x0000000000001010] <- 0x3FF0000000000000
Architectural state has not been committed.
Quick Understanding & Search Notes
RV32DC/RV64DC: add an unsigned byte offset (0–248, multiples of 8) to x[rs1']. On completion, store the low 64 bits of fs2'; source and base stay unchanged.
C.FSD is a real 16-bit CS encoding with FSD semantics.
The 3-bit rs1′ field maps to x8–x15; the 3-bit fs2′ field maps to f8–f15 in a separate register file.
Assembly offset is 0–248 bytes in multiples of 8; reconstruction implies 3 zero low bits. Do not rescale the assembly value.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — C 2.0The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — F 2.2 / D 2.2The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Zc 1.0The RISC-V Instruction Set Manual, Volume II: Privileged Architecture — Extension Context Status
Common Usage Scenarios
Floating-Point Memory Access
RV64DC, floating-point state enabled, x10=0x1000, low 64 bits of f8=0x7ff0000000000001, access completes: c.fsd f8, 0(x10) stores these 64 bits unchanged, leaving source and base unchanged.
Pre-Use Checklist
Syntax Check
- The 3-bit fs2′ field maps to f8–f15; the 3-bit rs1′ field maps to x8–x15 in the separate integer register file.
- offset is already an unsigned byte offset: 0–248, in multiples of 8, with 3 implied zero low bits. Do not scale it again.
Semantic Check
- RV32DC/RV64DC, floating-point state enabled, access permitted; store the low 64 source bits, preserving NaN payloads and leaving source and base unchanged.
- Address is base plus offset, wrapping at XLEN. Natural alignment raises no address-misaligned exception; misaligned outcomes are EEI-defined and an exception is not shown as a completed access.
Pitfalls / Common Confusions
This page uses RV32DC/RV64DC; D also depends on F.
Assembly offset is already 0–248 bytes in multiples of 8; do not scale it again.
Natural alignment raises no address-misaligned exception; the EEI defines whether misaligned accesses complete or raise an exception.
The transfer preserves NaN payloads; when FLEN exceeds 64, the store ignores upper bits and transfers only the low 64 bits.
FAQ
When is c.fsd available?
This page uses RV32DC/RV64DC, with floating-point state enabled and memory access permitted. C+D implies Zcd; Zcd depends on Zca and D, and D also depends on F.