Is the address register an FP register?
No. The base rs1 is an integer register; only the data source/destination is an FP register.
FLD
RISC-V FLD Instruction Details
Instruction ManualI-typeLoad 64-bit double-precision FP from memory into f register.
Instruction Syntax
fld rd, offset(rs1)
Operand Breakdown
rd: destination floating-point register.
rs1: integer base-address register.
offset: signed 12-bit byte offset added to rs1 to form the effective address.
DFloating-Point Load
Related Search Terms
Instruction Encoding
31..20
imm[11:0]
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
FLD uses opcode 0000111 (0x07), funct3 011. The rs1 field selects the integer base register, the immediate provides a byte offset, and rd selects the destination floating-point register.
Format: I-type
opcode: 0000111 (0x07)
funct3: 011 (0x3)
Instruction Behavior
FLD loads a 64-bit double-precision FP value from memory into f[rd] using base+offset addressing (I-type format). 12-bit signed immediate offset, base address in x[rs1]. The loaded value may be a NaN-boxed single-precision value. Only guaranteed atomic when naturally aligned and XLEN≥64. Bits are transferred unmodified; non-canonical NaN payloads preserved.
Quick Understanding & Search Notes
FLD is a floating-point load/store instruction. It forms the effective address from integer register rs1 plus a signed 12-bit offset and transfers the bit pattern between memory and an FP register.
The transfer width is 64 bits; D-extension double transfers do not interpret or canonicalize NaN payloads.
Atomicity of naturally aligned accesses and handling of misalignment are constrained by the spec and execution environment; this is not a synchronization primitive.
Common Usage Scenarios
Data Loading
Understand this scenario with real code like «fld f0, 0(x10)».
Pre-Use Checklist
Syntax Check
- rd: destination floating-point register.
- rs1: integer base-address register.
- offset: signed 12-bit byte offset added to rs1 to form the effective address.
Semantic Check
- Confirm offset is a byte offset, not an element index.
- Check natural alignment and the execution environment's misaligned-access rules.
Pitfalls / Common Confusions
misaligned: no atomicity guarantee on XLEN<64; on XLEN≥64, environment decides trap vs handle
offset is only 12-bit signed (±2KB range); compute address first for larger offsets
FAQ
What is the offset range?
The offset is a signed 12-bit immediate, encoding -2048 to 2047 bytes.