Is the FLD offset encoded in multiples of 8 bytes?
No. offset is a signed 12-bit byte offset; natural alignment is an address property, not the encoding unit.
FLD
RISC-V FLD Instruction Details
Instruction ManualI-typeLoad 64-bit double-precision FP from memory into f register.
Instruction Syntax
fld rd, offset(rs1)
Operand Breakdown
rd: destination floating-point register.
rs1: integer base-address register.
offset: signed 12-bit byte offset added to rs1 to form the effective address.
DFloating-Point Load
Instruction Behavior
FLD uses the I-type LOAD-FP encoding to load a 64-bit double-precision floating-point bit pattern from the effective address x[rs1] plus a signed 12-bit byte offset into floating-point register f[rd]. The transfer does not modify the bit pattern or canonicalize NaN payloads. FLD access atomicity is guaranteed by the official D-extension rule only when the effective address is naturally aligned and XLEN is at least 64; misaligned access is constrained by the execution environment.
FLD Decode And Execute Animation
Shows the D-extension FP load flow: decode the I-type encoding, form the address from an integer base plus a 12-bit offset, and transfer a 64-bit FP bit pattern.
rd
offset
rs1
fld
,
,
Execution Context
fmt=D / width=64
base register is an integer x register
fflags unchanged
31..20
19..15
14..12
11..7
6..0
000000010000
imm[11:0]
01010
rs1
011
FLD
01010
rd
0000111
LOAD-FP
Execution Data Path
instruction
0x01053507
opcode
0000111 -> LOAD-FP
funct3
011 -> 64-bit load
offset
000000010000 -> 16
rd/rs1
fa0(f10) / a0(x10)
read
a0(x10) = 0x0000000000001000
address
0x0000000000001000 + (16) = 0x0000000000001010
write
fa0(f10) = 0x400921FB54442D18
Current Step
Fetch: show the 32-bit I-type encoding
The word is split as a I-type instruction; FP memory access is not an OP-FP arithmetic encoding.
encoding: 0x01053507
syntax : fld fa0(f10), 16(a0(x10))
result : fa0(f10) = 0x400921FB54442D18
Address And Bit-Pattern Transfer
base
0x0000000000001000
offset
16
address
0x0000000000001010
loaded bits
0x400921FB54442D18
FLD transfers a 64-bit double-precision bit pattern; atomicity of naturally aligned access and misaligned handling follow the official spec and execution environment.
This animation shows only D-extension FP load/store ISA-visible address calculation and bit-pattern transfer; it does not model caches, buses, trap handlers, FPU pipelines, or microarchitectural timing.
Quick Understanding & Search Notes
FLD is the D-extension double-precision floating-point load. It forms the address from integer register rs1 plus a signed 12-bit byte offset, then loads a 64-bit double-precision bit pattern into FP register rd; the transfer performs no FP rounding.
I-type LOAD-FP: imm[11:0], rs1, funct3=011, rd, opcode=0000111.
Effective address = x[rs1] + sign_extend(offset), with the offset measured in bytes.
FLD transfers a 64-bit bit pattern; naturally aligned access is atomic when XLEN>=64.
Common Usage Scenarios
Data Loading
Understand this scenario with real code like «fld f0, 0(x10)».
Pre-Use Checklist
Syntax Check
- rd: destination floating-point register.
- rs1: integer base-address register.
- offset: signed 12-bit byte offset added to rs1 to form the effective address.
Semantic Check
- Confirm offset is a byte offset, not an element index.
- Check natural alignment and the execution environment's misaligned-access rules.
Pitfalls / Common Confusions
rs1 is an integer base register, and rd is the FP destination register.
offset is a signed 12-bit byte offset in -2048..2047.
FLD transfers a 64-bit double-precision bit pattern and performs no rounding or NaN payload canonicalization.
The atomicity guarantee requires natural alignment and XLEN>=64; do not treat misaligned FLD as a portable synchronization primitive.
FAQ
Does FLD change a NaN payload?
No. The official D extension states that load/store transfers do not modify the bits, so non-canonical NaN payloads are preserved.