What is the offset unit for c.fsw?
The encoded immediate is scaled by access width: 8 bytes for double-precision and 4 bytes for single-precision.
C.FSW
RISC-V C.FSW Instruction Details
Instruction ManualC-typeStore SP FP to memory. CS format, RV32FC.
Instruction Syntax
c.fsw fs2', offset(rs1')
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CFCompressed Instruction
Related Search Terms
Instruction Behavior
c.fsw in RV32FC, stores the 32-bit single-precision value from fs2' to rs1' plus a zero-extended offset scaled by 4.
Quick Understanding & Search Notes
c.fsw in RV32FC, stores the 32-bit single-precision value from fs2' to rs1' plus a zero-extended offset scaled by 4.
This is a real 16-bit C-extension memory encoding with semantics corresponding to the FLD/FLW/FSD/FSW floating-point load/store family.
C.FSW is defined only for RV32C; RV64C uses the same encoding space for C.SD.
The offset is zero-extended and scaled by access width in the encoding; it is not an arbitrary byte immediate.
Common Usage Scenarios
Compressed & Code Size
Understand this scenario with real code like «c.fsw f8, 0(x10)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is C-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
C.FSW is defined only for RV32C; RV64C uses the same encoding space for C.SD.
The offset is zero-extended and scaled by access width in the encoding; it is not an arbitrary byte immediate.
FAQ
Does c.fsw require a floating-point extension?
Yes. Double-precision forms require D, single-precision forms require F, and all require C.