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C.NOP

RISC-V C.NOP Instruction Details

Instruction ManualCI format

Fixed 16-bit no-operation. CI format; adjacent rd=x0, imm!=0 encodings are HINTs.

Instruction Syntax

c.nop
Operand Breakdown
c.nop has no explicit operands.
CI encoding fixes rd=x0, imm=0, funct3=000 and op=01, giving 0x0001.
Adjacent code points with rd=x0 and nonzero imm are HINTs; fixed fields do not imply register reads.
CZcaCompressed Instruction
Related Search Terms
C.NOP instructionc.nop encodingc.nop syntaxc.nop C/Zcac.nop HINTc.nop PC+2

Instruction Behavior

Ordinary C.NOP has the fixed 16-bit CI encoding 0x0001: funct3=000, rd=x0, imm=0, op=01, with no explicit operands. It changes no user-visible state except advancing PC by two bytes and incrementing applicable performance counters. It expands to nop (canonically addi x0, x0, 0). Code points with rd=x0 and nonzero imm in this space are HINTs. Available with RV32I/RV64I plus C or Zca.

C.NOP Decode And Execute Animation

RV32I/RV64I + C (or Zca); 16-bit, IALIGN=16.

c.nop

Execution Context

Assume successful instruction fetch, no asynchronous interrupt or extra extension checks; one initial value per register.

C.NOP: No register or memory write; only PC advancement and applicable performance-counter increments.
PC ← 0x00002002
16-bit encoding0x0001
funct3 [15..13]
000
imm[5] [12]
0
rd=x0 [11..7]
00000
imm[4:0] [6..2]
00000
op [1..0]
01
rd=x0; imm[5]|imm[4:0]=000000 → 0; C.NOP

Restore compressed operands

Restore full register fields or fixed operands; distinguish ordinary encodings, HINTs and reserved encodings first.

registers and memory unchanged; PC=0x00002000
Current architectural state (before commit)

These are teaching steps for architectural effects, not processor pipeline stages or cycles.

Quick Understanding & Search Notes

Fixed 16-bit no-operation. CI format; adjacent rd=x0, imm!=0 encodings are HINTs.

0x0001 comprises funct3=000, imm[5]=0, rd=x0, imm[4:0]=00000, and op=01.
HINTs do not modify architectural state except PC and applicable performance counters.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture (20260120)

Common Usage Scenarios

16-bit no-operation

RV32I/RV64I plus C/Zca, PC=0x2000: successful c.nop gives PC=0x2002, unchanged registers and memory, and applicable counter increments.

Pre-Use Checklist

Syntax Check
  • RV32I/RV64I plus C or Zca; 16-bit encoding, IALIGN=16.
  • Ordinary c.nop has no explicit operands; encoding 0x0001 fixes rd=x0 and imm=0.
Semantic Check
  • No register or memory writes; adjacent encodings with nonzero imm are HINTs.
  • Ordinary successful execution advances PC by 2; C.NOP/HINT still advances PC and applicable performance counters.

Pitfalls / Common Confusions

Ordinary c.nop has no explicit immediate operand; imm=0 is a fixed encoding field.
Adjacent encodings with rd=x0 and nonzero imm are HINTs.
No-operation still advances PC and applicable performance counters.

FAQ

Does C.NOP freeze PC?

No. Successful execution of 16-bit C.NOP advances PC by two bytes. Registers and memory remain unchanged, and applicable performance counters increment according to architectural rules.