C.ADDI
RISC-V C.ADDI Instruction Details
Instruction ManualC-typeAdd non-zero sign-extended 6-bit imm to rd. CI format.
Instruction Syntax
c.addi rd, imm
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Instruction Behavior
C.ADDI (CI format) adds non-zero sign-extended 6-bit immediate to rd, writes to rd. Expands to addi rd,rd,imm. HINT when rd≠x0 and imm=0. C.NOP when rd=x0 and imm=0 (HINT if imm≠0).
Common Usage Scenarios
Basic Arithmetic
Understand this scenario with real code like «c.addi x10, 5 # x10 += 5».
Loops & Iteration
Understand this scenario with real code like «c.addi x10, 5 # x10 += 5».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is C-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
imm=0 encodes HINT