What immediate range does C.ADDI encode?
The CI format combines imm[5] and imm[4:0] into a signed 6-bit immediate, so it represents -32 through 31; regular C.ADDI does not use zero.
C.ADDI
RISC-V C.ADDI Instruction Details
Instruction ManualCI formatRegular C.ADDI adds a nonzero sign-extended 6-bit immediate to a nonzero rd: rd += imm. CI format.
Instruction Syntax
c.addi rd, imm
Operand Breakdown
rd: full 5-bit destination/source field, x1–x31 for the regular form.
imm: imm[5] and imm[4:0] form an unscaled signed 6-bit value, sign-extended to XLEN; regular C.ADDI uses nonzero values from -32 through 31.
Nonzero rd with imm=0 is a HINT; rd=x0 selects the C.NOP encoding, whose nonzero immediates are HINTs.
CCompressed Instruction
Extension condition: C (or Zca) on RV32I/RV64I; 16-bit encoding, IALIGN=16. The animation assumes successful instruction fetch and no asynchronous interrupt.
Instruction Behavior
Regular C.ADDI uses the CI format to add a nonzero sign-extended 6-bit immediate to a nonzero rd and write rd; it expands to addi rd, rd, imm. Encodings with nonzero rd and imm=0 are HINTs. rd=x0 with imm=0 is C.NOP; C.NOP encodings with nonzero imm are also HINTs.
C.ADDI Execution Animation
RV32I/RV64I + C (or Zca), 16-bit encoding, IALIGN=16.
Instruction Syntax:
c.addi rd, immExecution Context
0x0000000C + (-5) (mod 2^32) = 0x00000007
x10 ← 0x00000007; PC ← 0x00002002
x10 ← 0x00000007; PC ← 0x00002002
16-bit Encoding
0x156D = 0001010101101101funct3 [15..13]
000
imm[5] [12]
1
rd [11..7]
01010 → x10
imm[4:0] [6..2]
11011
op [1..0]
01
imm[5]=1, imm[4:0]=11011
imm[5:0]=111011 → -5
Sign-extend to XLEN; no scaling
rd/rs1 → x10 = 0x0000000C
C.ADDI
imm[5:0]=111011 → -5
Sign-extend to XLEN; no scaling
rd/rs1 → x10 = 0x0000000C
C.ADDI
Restore compressed operands
Restore full register fields and the immediate, distinguishing ordinary instructions, HINTs, and shared encodings.
Current architectural state (before commit): x10=0x0000000C; PC=0x00002000
These are teaching steps for architectural effects, not processor pipeline stages or cycles.
Quick Understanding & Search Notes
C.ADDI is a 16-bit CI encoding for adding a signed 6-bit immediate to rd itself; the regular instruction form excludes rd=x0 and imm=0.
The immediate ranges from -32 to 31 and is sign-extended to XLEN before the addition.
Nonzero rd with imm=0 is a HINT. rd=x0 selects the C.NOP encoding: imm=0 is ordinary C.NOP and imm!=0 is a HINT. These do not perform ordinary C.ADDI writeback.
16-bit CI encoding: funct3[15:13]=000, imm[5] at bit 12, full 5-bit rd/rs1 at bits 11:7, imm[4:0] at bits 6:2, op[1:0]=01. The immediate is unscaled; addition retains only the low XLEN bits without an arithmetic-overflow exception.
Common Usage Scenarios
Basic Arithmetic
RV32I/RV64I + C/Zca, old x10=12: c.addi x10, -5 yields x10=7 after immediate sign extension and advances PC by 2.
Loops & Iteration
RV32I/RV64I + C/Zca, old x10=12: c.addi x10, -5 yields x10=7 after immediate sign extension and advances PC by 2.
Pre-Use Checklist
Syntax Check
- Verify C or Zca on RV32I/RV64I; these 16-bit encodings use full 5-bit register fields.
- The unscaled immediate is signed 6-bit, from -32 through 31; the regular form requires nonzero rd, and C.ADDI also excludes imm=0.
Semantic Check
- Distinguish ordinary writeback, HINTs, and shared encodings; do not present a HINT as ordinary arithmetic.
- Addition writes only the low XLEN bits; overlapping registers use one old value, and successful execution advances PC by 2.
Pitfalls / Common Confusions
Regular C.ADDI requires nonzero rd and nonzero imm; do not treat the imm=0 HINT as an addition.
rd=x0 with imm=0 is C.NOP, not regular C.ADDI.