Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
C.ADDI16SP
RISC-V C.ADDI16SP Instruction Details
Instruction ManualC-typeAdd 6-bit imm scaled by 16 to sp. CI format; shares opcode with C.LUI.
Instruction Syntax
c.addi16sp nzimm
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Instruction Behavior
C.ADDI16SP is the stack-pointer form of C.ADDI. It adds a nonzero signed immediate, encoded in 16-byte scaled form, to x2/sp. The effective immediate range is -512 to +496, and nzimm must not be zero.
Quick Understanding & Search Notes
C.ADDI16SP is the 16-bit encoding form for compressed add immediate to sp; its semantics and encodable register/immediate ranges must be read from the official C extension rules.
Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
Common Usage Scenarios
Function Call & Return
Understand this scenario with real code like «c.addi16sp -32 # sp -= 32».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is C-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
immediate must be non-zero
rd must be x2(sp)
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.