Why is the C.ADDI16SP immediate range not every integer?
The immediate is encoded with a 16-byte scale, so only nonzero multiples of 16 from -512 through 496 are encodable.
C.ADDI16SP
RISC-V C.ADDI16SP Instruction Details
Instruction ManualC-typeAdd a nonzero signed 6-bit immediate scaled by 16 to x2/sp. A 16-bit CI-format instruction sharing encoding space with C.LUI.
Operand notation
C.ADDI16SP: nzimm (x2/sp fixed)
Operand Breakdown
16-bit CI format; rd/rs1 is fixed to x2/sp, with no x8–x15 mapping.
The nonzero immediate is a multiple of 16 from -512 through 496; the zero encoding is reserved.
Sign-extend and add to the old sp, retaining the low XLEN bits; this corresponds to addi x2, x2, nzimm.
CCompressed Instruction
Instruction Behavior
C.ADDI16SP shares encoding space with C.LUI but fixes the destination field to x2/sp. It sign-extends scattered nonzero nzimm[9:4] and adds it to x2/sp; this immediate represents 16-byte multiples from -512 through 496. It expands to addi x2, x2, nzimm[9:4]; the nzimm=0 encoding is reserved.
C.ADDI16SP Decode And Execute Animation
Read and write fixed x2/sp, restore the scaled immediate, then calculate and commit the XLEN-bit result.
Fixed source and destination
x2 / sp
x2/sp: 0x00001000 + -32 → 0x00000FE0
0x713D = 0111000100111101 (CI)
funct3 [15..13]
011
nzimm[9] [12]
1
rd/rs1 [11..7]
00010 (x2/sp)
nzimm[4|6|8:7|5] [6..2]
01111
op [1..0]
01
nzimm[9:4] = 111110
Sign-extend and scale: -2 × 16 = -32
Not computed
Restore compressed operands
rd/rs1 is fixed to 00010. inst[12] and inst[6:2] restore nzimm[9:4]; the low four bits are zero and the immediate is sign-extended to XLEN.
x2/sp = 0x00001000; PC = 0x00002000
Assumes C is available and instruction fetch succeeds. Teaching steps do not represent processor pipelines or cycles; multiples of 16 preserve the original low four bits of sp and do not repair a misaligned sp.
Quick Understanding & Search Notes
C.ADDI16SP is a 16-bit C-extension instruction: it reads and writes fixed x2/sp and adds sign-extended nonzero nzimm[9:4]. It encodes only 16-byte multiples from -512 through 496.
funct3=011, op=01, and the rd field is x2; nzimm is scattered as [9] and [4|6|8:7|5].
nzimm=0 is a reserved encoding and must not be presented as ordinary C.ADDI16SP arithmetic or a stack-frame adjustment.
Common Usage Scenarios
Function Call & Return
A function prologue or epilogue can adjust fixed x2/sp by a nonzero multiple of 16; with old sp=0x1000 and nzimm=-32, successful execution gives sp=0x0fe0, equivalent to addi x2, x2, -32.
Pre-Use Checklist
Syntax Check
- Confirm RV32C / RV64C and the 16-bit encoding conditions.
- 16-bit CI format; rd/rs1 is fixed to x2/sp, with no x8–x15 mapping.
Semantic Check
- The nonzero immediate is a multiple of 16 from -512 through 496; the zero encoding is reserved.
- Sign-extend and add to the old sp, retaining the low XLEN bits; this corresponds to addi x2, x2, nzimm.
Pitfalls / Common Confusions
The immediate must be a nonzero multiple of 16 from -512 through 496; nzimm=0 is reserved.
x2/sp is the fixed implicit source and destination register, not a selectable rd.
FAQ
What happens when nzimm=0?
C.ADDI16SP is valid only when nzimm is nonzero; the nzimm=0 encoding is reserved.