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C.ADDI4SPN

RISC-V C.ADDI4SPN Instruction Details

Instruction ManualC-type

Add zero-extended non-zero imm scaled by 4 to sp, result to rd'. CIW format.

Instruction Syntax

c.addi4spn rd', imm
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Related Search Terms
C.ADDI4SPN instructionRISC-V C.ADDI4SPNc.addi4spn syntaxc.addi4spn encodingc.addi4spn Cc.addi4spn compressed instructioncompressed add sp plus nonzero immediate

Instruction Behavior

C.ADDI4SPN (CIW format) adds zero-extended non-zero immediate scaled by 4 to sp(x2), writes to rd' (x8-x15 only). Expands to addi rd',x2,nzuimm[9:2]. Valid only when nzuimm≠0. Used to generate pointers to stack-allocated variables.

Quick Understanding & Search Notes

C.ADDI4SPN is the 16-bit encoding form for compressed add sp plus nonzero immediate; its semantics and encodable register/immediate ranges must be read from the official C extension rules.

Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
RISC-V Unprivileged ISA Manual, C Extension

Common Usage Scenarios

Address & Pointer

Understand this scenario with real code like «c.addi4spn x8, 16 # x8 = sp+16».

Function Call & Return

Understand this scenario with real code like «c.addi4spn x8, 16 # x8 = sp+16».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is C-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

immediate must be non-zero
destination only x8-x15

FAQ

Is it always equivalent to a same-named 32-bit instruction?

Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.

Why do register restrictions matter?

Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.