Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
C.ADDI4SPN
RISC-V C.ADDI4SPN Instruction Details
Instruction ManualC-typeAdd zero-extended non-zero imm scaled by 4 to sp, result to rd'. CIW format.
Instruction Syntax
c.addi4spn rd', nzuimm
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Instruction Behavior
C.ADDI4SPN (CIW format) adds zero-extended non-zero immediate scaled by 4 to sp(x2), writes to rd' (x8-x15 only). Expands to addi rd',x2,nzuimm[9:2]. Valid only when nzuimm≠0. Used to generate pointers to stack-allocated variables.
C.ADDI4SPN Compressed Encoding Lab
Connect 16-bit fields to compressed constraints, base-instruction semantics, and visible architectural state.
c.addi4spn,
Input
sp = 0x0000000000001000, offset = 16+
Result
x8 = 0x000000000000101016-bit encoding and field roles
15..13
000
funct3
12..11
01
nzuimm[5:4]
10..7
0000
nzuimm[9:6]
6 / 5
0 / 0
[2] / [3]
4..2
000
rd' -> x8
1..0
00
C0
Visible calculation
sp / x2
0x0000000000001000
+
nzuimm
16 (0x0000000000000010)
=
x8
0x0000000000001010
Fixed x2 is the input base; rd' is the sole writeback target.
Field reconstruction and address generation
Compressed register map
rd' -> x8 (x8-x15)Scattered immediate
nzuimm[9:2] = 00000100; low bits = 00Base semantic comparison
addi x8, x2, 16Commit
x8 <- 0x0000000000001010Architectural state has not been committed.
Quick Understanding & Search Notes
C.ADDI4SPN is the 16-bit encoding form for compressed add sp plus nonzero immediate; its semantics and encodable register/immediate ranges must be read from the official C extension rules.
Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
Common Usage Scenarios
Address & Pointer
Understand this scenario with real code like «c.addi4spn x8, 16 # x8 = sp+16».
Compressed & Code Size
Understand this scenario with real code like «c.addi4spn x8, 16 # x8 = sp+16».
Pre-Use Checklist
Syntax Check
- Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
- Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
- Note the limited operand space of compressed instructions.
- Verify this compressed instruction has a corresponding 32-bit expansion.
Pitfalls / Common Confusions
immediate must be nonzero and a multiple of 4 (4 through 1020)
destination only x8-x15
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.