Does it modify sp?
No. Fixed x2/sp is the source and only rd' is written; with sp=0x1000 and offset 16, x8=0x1010.
C.ADDI4SPN
RISC-V C.ADDI4SPN Instruction Details
Instruction ManualC-typeRV32/RV64: add a nonzero byte offset (4–1020, multiples of four) to sp and write x8–x15; sp is unchanged.
Instruction Syntax
c.addi4spn rd', nzuimm
Operand Breakdown
RV32/RV64, C 2.0 or Zca; 16-bit CIW format.
The three-bit rd' field selects x8–x15; the source is fixed x2/sp and the byte offset is a nonzero multiple of four from 4 through 1020.
Add the zero-extended offset to old sp and write the low XLEN bits to rd'; sp is unchanged. Zero offset is reserved.
CCompressed Instruction
Instruction Behavior
C.ADDI4SPN is a 16-bit CIW instruction in C 2.0 / Zca. It reads fixed x2/sp, adds the zero-extended byte offset nzuimm, and writes rd' (x8–x15). The assembly offset is already in bytes, so do not multiply it by four again; the eight encoded bits represent nzuimm[9:2], with two zero low bits. Keep the low XLEN bits, as in addi rd', x2, nzuimm. nzuimm=0 is reserved; sp is unchanged.
C.ADDI4SPN Compressed Encoding Lab
Connect 16-bit fields to compressed constraints, base-instruction semantics, and visible architectural state.
c.addi4spn,
Input
sp = 0x0000000000001000, offset = 16+
Result
x8 = 0x0000000000001010RV32C/RV64C / Zca; IALIGN=16
16-bit encoding and field roles
15..13
000
funct3
12..11
01
nzuimm[5:4]
10..7
0000
nzuimm[9:6]
6 / 5
0 / 0
[2] / [3]
4..2
000
rd' -> x8
1..0
00
C0
Visible calculation
sp / x2
0x0000000000001000
+
nzuimm
16 (0x0000000000000010)
=
x8
0x0000000000001010
Fixed x2 is the input base; rd' is the sole writeback target.
Field reconstruction and address generation
Compressed register map
rd' -> x8 (x8-x15)Scattered immediate
nzuimm[9:2] = 00000100; low bits = 00Base semantic comparison
addi x8, x2, 16Commit
x8 <- 0x0000000000001010Architectural state has not been committed.
Quick Understanding & Search Notes
RV32/RV64: add a nonzero byte offset (4–1020, multiples of four) to sp and write x8–x15; sp is unchanged.
CIW: funct3=000, op=00; immediate field order is [5:4|9:6|2|3], with a three-bit rd'.
Available on RV32/RV64; rd' is x8–x15 and the byte offset is a multiple of four from 4 through 1020.
Common Usage Scenarios
Address & Pointer
RV32/RV64, sp=0x1000: c.addi4spn x8, 16 gives x8=0x1010, leaving sp unchanged; 16 is already the byte offset.
Compressed & Code Size
RV32/RV64, sp=0x1000: c.addi4spn x8, 16 gives x8=0x1010, leaving sp unchanged; 16 is already the byte offset.
Pre-Use Checklist
Syntax Check
- RV32/RV64, C 2.0 or Zca; 16-bit CIW format.
- The three-bit rd' field selects x8–x15; the source is fixed x2/sp and the byte offset is a nonzero multiple of four from 4 through 1020.
Semantic Check
- Add the zero-extended offset to old sp and write the low XLEN bits to rd'; sp is unchanged. Zero offset is reserved.
Pitfalls / Common Confusions
immediate must be nonzero and a multiple of 4 (4 through 1020)
destination only x8-x15
FAQ
Should an assembly offset of 16 be multiplied by four?
No. 16 is already the byte offset; the encoding stores bits [9:2] and restores two zero low bits. Zero offset is reserved.