RISC-V C.ADD Instruction Details

Instruction ManualC-type

Add rd and rs2, write to rd. CR format. rs2!=x0.

Instruction Syntax

c.add rd, rs2

Operand Breakdown

Compressed instructions are 16 bits; registers are often limited to x8–x15.

Immediate fields are narrower. Refer to the full encoding for this compressed instruction.

CCompressed Instruction

Related Search Terms

C.ADD instruction RISC-V C.ADD c.add syntax c.add encoding c.add C-type c.add compressed instruction

Instruction Behavior

C.ADD (CR format, all 32 registers accessible) adds rd and rs2, writes to rd. Expands to add rd,rd,rs2. rs2≠x0; rs2=x0 is C.JALR/C.EBREAK. HINT when rd=x0 and rs2≠x0.

Common Usage Scenarios

Basic Arithmetic

Understand this scenario with real code like «c.add x10, x11 # x10 += x11».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is C-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

rs2 cannot be x0 (encodes C.JALR or C.EBREAK)

CR format allows all 32 registers (unlike C.AND etc. in CA format limited to x8-x15)