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C.ADD

RISC-V C.ADD Instruction Details

Instruction ManualCR format

Regular C.ADD adds rd and rs2 and writes the result to rd. CR format; both rd and rs2 must be nonzero.

Instruction Syntax

c.add rd, rs2
Operand Breakdown
This is a CR format-format instruction. Confirm operand positions based on the assembly syntax.
CCompressed Instruction
Related Search Terms
C.ADD instructionRISC-V C.ADDc.add syntaxc.add encodingc.add CR formatc.add compressed instruction

Instruction Behavior

C.ADD (CR format, with access to all 32 registers) adds rd and rs2 and writes the result to rd, equivalent to add rd, rd, rs2. Regular C.ADD requires rd!=x0 and rs2!=x0: with rs2=x0, rd!=x0 encodes C.JALR and rd=x0 encodes C.EBREAK. With nonzero rs2 and rd=x0, the encoding is normally a HINT; when Zihintntl is implemented, rs2=x2-x5 instead encode C.NTL.P1, C.NTL.PALL, C.NTL.S1, and C.NTL.ALL.

C.ADD Decode And Execute Animation

Decodes the real 16-bit CR or CI encoding and distinguishes normal instructions, HINTs, and shared encodings.

Current Step

Step 1: identify C.ADD

funct4, rd/rs1, rs2, and op together identify this 16-bit C.ADD instruction.

Instruction Syntax
Execution Context
16-bit Encoding
0x952E = 1001010100101110
funct4 [15..12]
1001
rd/rs1 [11..7]
01010
rs2 [6..2]
01011
op [1..0]
10
C.ADD Execution Path

x[rd] ← old x[rd] + x[rs2] (write back only the low XLEN bits)

rd is both the first source and the destination: old x[rd] is read before the result overwrites it.

1. Decode CR fields

funct4=1001 and op=10; rd/rs1=x10, rs2=x11. Both are nonzero, so this is ordinary C.ADD.

2. Read the pre-writeback snapshot

Registers have not been read yet; x[rd] must not be overwritten.

3. Add at XLEN width

No calculation yet; read both source values first.

4. Write back rd

No writeback yet; the architecturally visible x[rd] is still the old snapshot.

This animation shows only officially defined decode, register reads, arithmetic, and architectural state, not a particular implementation's pipeline, cache, prediction, or timing.

Quick Understanding & Search Notes

C.ADD uses the CR format and writes rd + rs2 back to rd; the regular C.ADD form requires both rd and rs2 not to be x0.

C.ADD expands to add rd, rd, rs2 and uses full 5-bit rd and rs2 register fields.
With rs2=x0, rd!=x0 decodes as C.JALR and rd=x0 as C.EBREAK. With rd=x0 and nonzero rs2, the encoding is normally a HINT; under Zihintntl, rs2=x2-x5 instead encode C.NTL.P1/PALL/S1/ALL.
RISC-V Unprivileged ISA Manual: C extension, Section 28.5.3 (Integer Register-Register Operations)

Common Usage Scenarios

Basic Arithmetic

Understand this scenario with real code like «c.add x10, x11 # x10 += x11».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is CR format.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

rs2=x0 is not C.ADD: rd!=x0 encodes C.JALR and rd=x0 encodes C.EBREAK; rd=x0 with rs2=x2-x5 is a C.NTL encoding under Zihintntl.
CR format allows all 32 registers (unlike C.AND etc. in CA format limited to x8-x15)

FAQ

Which registers can C.ADD use?

The CR-format rd and rs2 fields are full 5-bit fields, so the encoding can name registers x0-x31; regular C.ADD semantics require both rd and rs2 not to be x0.