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C.MV

RISC-V C.MV Instruction Details

Instruction ManualCR format

Copy rs2 into rd. CR format; rs2 must not be x0.

Instruction Syntax

c.mv rd, rs2
Operand Breakdown
This is a CR format-format instruction. Confirm operand positions based on the assembly syntax.
CCompressed Instruction
Related Search Terms
C.MV instructionRISC-V C.MVc.mv syntaxc.mv encodingc.mv CR formatc.mv compressed instruction

Instruction Behavior

C.MV uses the CR format to copy rs2 to rd, with the base-instruction semantics of add rd, x0, rs2. rs2 must not be x0; an rs2=x0 encoding is C.JR. An encoding with rd=x0 and rs2!=x0 is a HINT.

C.MV Decode And Execute Animation

Decodes the real 16-bit CR or CI encoding and distinguishes normal instructions, HINTs, and shared encodings.

Current Step

Step 1: identify C.MV

The animation shows C-extension 16-bit fields directly instead of pretending this is a 32-bit scalar instruction.

Instruction Syntax
Execution Context
16-bit Encoding
0x852E = 1000010100101110
funct4 [15..12]
1000
rd/rs1 [11..7]
01010
rs2 [6..2]
01011
op [1..0]
10
Operands And Calculation
x11 = 0x00000009
Copy the complete XLEN-bit value; perform no arithmetic.
rd ← rs2
Decoded Result And Architectural State
C.MV

x10 = 0x00000009

This animation shows only officially defined decode, register reads, arithmetic, and architectural state, not a particular implementation's pipeline, cache, prediction, or timing.

Common Usage Scenarios

Register Operations

Understand this scenario with real code like «c.mv x10, x11 # x10 = x11».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is CR format.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

rs2!=x0 (x0 = C.JR)