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C.MV

RISC-V C.MV Instruction Details

Instruction ManualCR format

16-bit register copy: the ordinary form copies the full XLEN-bit value of nonzero rs2 to nonzero rd.

Instruction Syntax

c.mv rd, rs2
Operand Breakdown
rd: full 5-bit destination field, x1–x31 in the ordinary form; old rd is not a source.
rs2: full 5-bit source field, x1–x31 in the ordinary form; all XLEN bits are copied.
rs2=x0 with nonzero rd selects C.JR; both zero is reserved; rd=x0 with nonzero rs2 is a HINT.
CZcaCompressed Instruction
Related Search Terms
C.MV instructionc.mv encodingc.mv syntaxc.mv C/Zcac.mv HINTc.mv full registers

Instruction Behavior

C.MV is a 16-bit CR-format instruction with full 5-bit rd and rs2 fields. It copies all XLEN bits of rs2 to rd and expands to add rd, x0, rs2. The ordinary form requires nonzero rd and rs2. With rs2=x0 and nonzero rd, the encoding is C.JR; with both zero it is reserved. Nonzero rs2 with rd=x0 is a HINT. Available with RV32I/RV64I plus C or Zca.

C.MV Decode And Execute Animation

RV32I/RV64I + C (or Zca); 16-bit, IALIGN=16.

c.mv rd, rs2

Execution Context

Assume successful instruction fetch, no asynchronous interrupt or extra extension checks; one initial value per register.

0 + 0x00000009 = 0x00000009; x10 ← 0x00000009
PC ← 0x00002002
16-bit encoding0x852E
funct4 [15..12]
1000
rd [11..7]
01010 → x10
rs2 [6..2]
01011 → x11
op [1..0]
10
rd[4:0]=01010 → x10; rs2[4:0]=01011 → x11=0x00000009; C.MV

Restore compressed operands

Restore full register fields or fixed operands; distinguish ordinary encodings, HINTs and reserved encodings first.

x10=0x00000007; PC=0x00002000
Current architectural state (before commit)

These are teaching steps for architectural effects, not processor pipeline stages or cycles.

Quick Understanding & Search Notes

16-bit register copy: the ordinary form copies the full XLEN-bit value of nonzero rs2 to nonzero rd.

funct4=1000 and op=10; rd occupies bits 11..7 and rs2 bits 6..2.
The ordinary copy does not read old rd; rd=rs2 still uses the pre-writeback source value.
Ordinary successful execution advances PC by 2; HINTs only advance PC and applicable performance counters.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture (20260120)

Common Usage Scenarios

Register Operations

RV32I/RV64I plus C/Zca, x11=9: c.mv x10, x11 gives x10=9 and PC+2; old x10 is not a source.

Pre-Use Checklist

Syntax Check
  • RV32I/RV64I plus C or Zca; 16-bit encoding, IALIGN=16.
  • CR rd and rs2 are full 5-bit fields, both nonzero for the ordinary form; they are not compact x8–x15 fields.
Semantic Check
  • Copy all XLEN bits of rs2 without reading old rd; rs2=x0 selects C.JR, reserved when rd=x0; rd=x0 with nonzero rs2 is a HINT.
  • Ordinary successful execution advances PC by 2; C.NOP/HINT still advances PC and applicable performance counters.

Pitfalls / Common Confusions

rd and rs2 are full 5-bit fields, not limited to x8–x15.
rs2=x0 with nonzero rd selects C.JR; rd=rs2=x0 is reserved.
rd=x0 with nonzero rs2 is a HINT, not an ordinary register copy.

FAQ

Does C.MV expand like MV?

No. C.MV expands to add rd, x0, rs2; canonical MV expands to addi rd, rs, 0. Both copy a register value.

Can rd and rs2 overlap?

Yes. With nonzero rd=rs2, one old value is read and written back, leaving the register bit pattern unchanged.