Why does C.JR clear target bit 0?
It has jalr x0, 0(rs1) semantics; JALR clears bit 0 after forming its target.
C.JR
RISC-V C.JR Instruction Details
Instruction ManualC-typeJump via register: target is rs1 with bit 0 cleared. CR format. rs1!=x0.
Instruction Syntax
c.jr rs1
Operand Breakdown
C.JR uses the 16-bit CR format; its full 5-bit rs1 selects x1-x31, with rs1=x0 reserved.
The rs2 field is fixed to 00000; it corresponds to jalr x0, 0(rs1), without an explicit immediate.
The target is x[rs1] with bit 0 cleared; no link register is written.
CCompressed Instruction
Extension condition: RV32C / RV64C; this page describes C extension version 2.0.
Instruction Behavior
C.JR (CR format) jumps with the semantics of jalr x0, 0(rs1): its target comes from rs1 with bit 0 cleared. It is valid only when rs1!=x0 (rs1=x0 is reserved) and saves no return address.
C.JR Instruction Animation
Three learning stages illustrate architectural rules, without modeling processor pipelines or cycles.
c.jr
Execution context
RV32C / RV64C; C sets IALIGN=16, so PC is an even byte address. Address arithmetic wraps at XLEN. Subsequent target instruction-fetch exceptions are outside this model.
c.jr → PC ← 0x00002000; no link register write
16-bit encoding fields
0x8082
15..12
funct4
1000
11..7
rs1
00001
6..2
rs2
00000
1..0
op
10
Operands and calculation
Restore compressed operands
rs1=00001 → x1; rs2=00000; rd=x0; imm=0
Calculate
Not computed
Commit result
Pending commit
Architectural result
Architectural result not committed yet.
Quick Understanding & Search Notes
C.JR uses CR format and has jalr x0, 0(rs1) semantics: it clears target bit 0 and writes no return address.
rs1 must not be x0; that encoding is reserved.
C.JR uses the full 5-bit rs1 field rather than being limited to x8-x15.
Common Usage Scenarios
Indirect Jump & Return
Understand this scenario with real code like «c.jr ra # ra=x1=0x2001 -> PC=0x2000; no link write».
Pre-Use Checklist
Syntax Check
- Confirm RV32C / RV64C and the 16-bit encoding conditions.
- C.JR uses the 16-bit CR format; its full 5-bit rs1 selects x1-x31, with rs1=x0 reserved.
Semantic Check
- The rs2 field is fixed to 00000; it corresponds to jalr x0, 0(rs1), without an explicit immediate.
- The target is x[rs1] with bit 0 cleared; no link register is written.
Pitfalls / Common Confusions
The rs1=x0 encoding is reserved, not C.JR.
The full 5-bit rs1 selects x1-x31, without the x8-x15 restriction.
Target bit 0 is cleared; C sets IALIGN=16, so the target need not be a multiple of 4.