Why does C.JR clear target bit 0?
It has jalr x0, 0(rs1) semantics; JALR clears bit 0 after forming its target.
C.JR
RISC-V C.JR Instruction Details
Instruction ManualC-typeJump via register: target is rs1 with bit 0 cleared. CR format. rs1!=x0.
Instruction Syntax
c.jr rs1
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Instruction Behavior
C.JR (CR format) jumps with the semantics of jalr x0, 0(rs1): its target comes from rs1 with bit 0 cleared. It is valid only when rs1!=x0 (rs1=x0 is reserved) and saves no return address.
C.JR Decode & Execute Animation
This interactive model shows only architectural decode, operands, and state changes, not a pipeline, cache, or timing model.
c.jr
Execution context
Encoding fields
15..12
funct4
1000
11..7
rs1
00001
6..2
rs2
00000
1..0
op
10
Execution data path
Decode
CR: funct4 / rs1 / rs2=0
Operands
x1 = 0x00002001
Execute
0x00002001 & ~1
State
PC <- 0x00002000
C.JR does not write a link register.
Architectural result
Awaiting state update: the highlighted fields and calculation above show the current step; no architectural result has been committed yet.
Quick Understanding & Search Notes
C.JR uses CR format and has jalr x0, 0(rs1) semantics: it clears target bit 0 and writes no return address.
rs1 must not be x0; that encoding is reserved.
C.JR uses the full 5-bit rs1 field rather than being limited to x8-x15.
Common Usage Scenarios
Indirect Jump & Return
Understand this scenario with real code like «c.jr ra # return».
Pre-Use Checklist
Syntax Check
- Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
- Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
- Note the limited operand space of compressed instructions.
- Verify this compressed instruction has a corresponding 32-bit expansion.
Pitfalls / Common Confusions
rs1 cannot be x0