Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
C.JALR
RISC-V C.JALR Instruction Details
Instruction ManualC-typeJump via register; write pc+2 to x1. CR format. rs1!=x0.
Instruction Syntax
c.jalr rs1
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Instruction Behavior
C.JALR (CR format) jumps to address in rs1, writes pc+2 to x1(ra). Expands to jalr x1,0(rs1). Valid only when rs1≠x0 (rs1=x0 is C.EBREAK). Link address offset is 2 bytes (vs 4 bytes for 32-bit Jalr).
Quick Understanding & Search Notes
C.JALR is the 16-bit encoding form for compressed jump and link register; its semantics and encodable register/immediate ranges must be read from the official C extension rules.
Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
Common Usage Scenarios
Function Call & Return
Understand this scenario with real code like «c.jalr ra # call *ra, retaddr to ra».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is C-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
rs1!=x0 (x0 = C.EBREAK)
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.