Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
C.JALR
RISC-V C.JALR Instruction Details
Instruction ManualC-typeJump via register; write pc+2 to x1. CR format. rs1!=x0.
Instruction Syntax
c.jalr rs1
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Instruction Behavior
C.JALR (CR format) jumps to the rs1 target with its least-significant bit cleared and writes pc+2 to x1 (ra). It expands to jalr x1, 0(rs1). It is valid only when rs1 is not x0 (rs1=x0 is C.EBREAK); its link offset is 2 bytes, not the 4 bytes of a 32-bit JALR.
C.JALR Compressed Encoding Lab
Connect 16-bit fields to compressed constraints, base-instruction semantics, and visible architectural state.
c.jalr
Before jump
PC = 0x0000000000001000, x1 = 0x0000000000002001->
Architectural result
PC = 0x0000000000002000; x1 = 0x000000000000100216-bit encoding and field roles
15..12
1001
funct4
11..7
00001
rs1 -> x1
6..2
00000
fixed rs2
1..0
10
C2
Visible calculation
x[rs1]
0x0000000000002001
& ~1
new PC
0x0000000000002000
PC
0x0000000000001000
+ 2
x1 / ra
0x0000000000001002
The target clears bit 0 and the link uses the compressed 2-byte length.
Control-flow path
CR fields
1001 00001 00000 10Target normalization
x[rs1] & ~1 -> 0x0000000000002000Base semantic comparison
jalr x1, 0(x1)Link and jump commit
pc <- 0x0000000000002000; x1/ra <- 0x0000000000001002Architectural state has not been committed.
Quick Understanding & Search Notes
C.JALR is the 16-bit encoding form for compressed jump and link register; its semantics and encodable register/immediate ranges must be read from the official C extension rules.
Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
Common Usage Scenarios
Function Call & Return
Understand this scenario with real code like «c.jalr ra # call *ra, retaddr to ra».
Pre-Use Checklist
Syntax Check
- Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
- Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
- Note the limited operand space of compressed instructions.
- Verify this compressed instruction has a corresponding 32-bit expansion.
Pitfalls / Common Confusions
rs1 must not be x0 (that encoding is C.EBREAK)
The JALR target clears bit 0; the link address is pc+2
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.