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C.ADDW

RISC-V C.ADDW Instruction Details

Instruction ManualCA-format

32-bit add with sign-extend to 64. CA format, RV64C.

Instruction Syntax

c.addw rd', rs2'
Operand Breakdown
This is a CA-format-format instruction. Confirm operand positions based on the assembly syntax.
CCompressed Instruction
Related Search Terms
c.addw instructionc.addw syntaxRV64C c.addwc.addw sign extendc.addw rd rs2

Instruction Behavior

c.addw is an RV64C CA-format instruction. It adds rd' and rs2' as 32-bit values, sign-extends bit 31 to XLEN, and writes rd'.

C.ADDW Decode & Execute Animation

Shows only manual-defined 16-bit fields, operands, and ISA-visible results; it does not model a pipeline, cache, timing, or an implementation's memory-fault handling.

c.addw,
Execution context
x8 = 0xFFFFFFFF80000000; x9 = 0x0000000000000001 -> 0x80000001 -> sext.w -> 0xFFFFFFFF80000001 -> x8 = 0xFFFFFFFF80000001
16-bit encoding fields
15..10
funct6
100111
9..7
rd'/rs1'
000
6..5
funct2
01
4..2
rs2'
001
1..0
op
01
Execution data path
x8 = 0xFFFFFFFF80000000; x9 = 0x0000000000000001
0x80000001 -> sext.w -> 0xFFFFFFFF80000001
x8 <- 0xFFFFFFFF80000001
Architectural state has not been committed.

Quick Understanding & Search Notes

c.addw is an RV64C CA-format instruction. It adds rd' and rs2' as 32-bit values, sign-extends bit 31 to XLEN, and writes rd'.

Compressed instructions usually mirror a 32-bit base instruction semantic, but with register-subset, immediate-encoding, or XLEN restrictions.
This W form is defined for RV64C, not RV32C.
rd' and rs2' use the compressed register subset x8..x15.
RISC-V Unprivileged ISA Manual, C compressed extension

Common Usage Scenarios

Compressed & Code Size

Understand this scenario with real code like «c.addw x8, x9 # x8 = sext_w(x8+x9)».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is CA-format.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

This W form is defined for RV64C, not RV32C.
rd' and rs2' use the compressed register subset x8..x15.

FAQ

Why does c.addw have register restrictions?

Many C formats encode registers with shorter fields, so some forms can access only x8..x15 or fixed registers.

Is c.addw just an assembler pseudo-instruction?

No. It is a 16-bit encoded instruction defined by the C extension.