Why does c.addw have register restrictions?
Many C formats encode registers with shorter fields, so some forms can access only x8..x15 or fixed registers.
C.ADDW
RISC-V C.ADDW Instruction Details
Instruction ManualC-type32-bit add with sign-extend to 64. CA format, RV64C.
Instruction Syntax
c.addw rd', rs2'
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Related Search Terms
Instruction Behavior
c.addw is an RV64C CA-format instruction. It adds rd' and rs2' as 32-bit values, sign-extends bit 31 to XLEN, and writes rd'.
Quick Understanding & Search Notes
c.addw is an RV64C CA-format instruction. It adds rd' and rs2' as 32-bit values, sign-extends bit 31 to XLEN, and writes rd'.
Compressed instructions usually mirror a 32-bit base instruction semantic, but with register-subset, immediate-encoding, or XLEN restrictions.
This W form is defined for RV64C, not RV32C.
rd' and rs2' use the compressed register subset x8..x15.
Common Usage Scenarios
Compressed & Code Size
Understand this scenario with real code like «c.addw x8, x9 # x8 = sext_w(x8+x9)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is C-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
This W form is defined for RV64C, not RV32C.
rd' and rs2' use the compressed register subset x8..x15.
FAQ
Is c.addw just an assembler pseudo-instruction?
No. It is a 16-bit encoded instruction defined by the C extension.