Why does c.addw have register restrictions?
Many C formats encode registers with shorter fields, so some forms can access only x8..x15 or fixed registers.
C.ADDW
RISC-V C.ADDW Instruction Details
Instruction ManualCA-format32-bit add with sign-extend to 64. CA format, RV64C.
Instruction Syntax
c.addw rd', rs2'
rd′ selects x8–x15 and is both the old source and the writeback destination; read the old value before writing.
rs2′ also selects x8–x15; equal source names have one old value.
RV64C: retain the low 32-bit sum, then sign-extend to 64 bits; this is not a full 64-bit sum.
CCompressed Instruction
Related Search Terms
Instruction Behavior
A 16-bit RV64C CA instruction: add x[rd'] and x[rs2'], sign-extend the low 32-bit sum to 64 bits, and write rd'. Both registers are x8–x15.
C.ADDW Decode & Execute Animation
Shows only manual-defined 16-bit fields, operands, and ISA-visible results; it does not model a pipeline, cache, timing, or an implementation's memory-fault handling.
c.addw,
Execution context
Scope: RV64C, 16-bit CA encoding.
x8 = 0xFFFFFFFF80000000; x9 = 0x0000000000000001 -> (0x80000000 + 0x00000001) mod 2^32 = 0x80000001 -> sext.w -> 0xFFFFFFFF80000001 -> x8 = 0xFFFFFFFF80000001
16-bit encoding fields
rd'=000 -> x8; rs2'=001 -> x9
15..10
funct6
100111
9..7
rd'/rs1'
000
6..5
funct2
01
4..2
rs2'
001
1..0
op
01
Execution data path
x8 = 0xFFFFFFFF80000000; x9 = 0x0000000000000001
(0x80000000 + 0x00000001) mod 2^32 = 0x80000001 -> sext.w -> 0xFFFFFFFF80000001
x8 <- 0xFFFFFFFF80000001
Architectural state has not been committed.
Quick Understanding & Search Notes
A 16-bit RV64C CA instruction: add x[rd'] and x[rs2'], sign-extend the low 32-bit sum to 64 bits, and write rd'. Both registers are x8–x15.
C.ADDW is a real 16-bit encoding with ADDW semantics; the destination also supplies the old first source value.
This W form is defined for RV64C, not RV32C.
rd' and rs2' use the compressed register subset x8..x15.
Common Usage Scenarios
Sign-extend a 32-bit sum
RV64C, old x8=0x7fffffff and x9=1: c.addw x8, x9 produces low sum 0x80000000 and writes x8=0xffffffff80000000.
Pre-Use Checklist
Syntax Check
- rd′ selects x8–x15 and is both the old source and the writeback destination; read the old value before writing.
- rs2′ also selects x8–x15; equal source names have one old value.
Semantic Check
- RV64C: retain the low 32-bit sum, then sign-extend to 64 bits; this is not a full 64-bit sum.
Pitfalls / Common Confusions
This W form is defined for RV64C, not RV32C.
rd' and rs2' use the compressed register subset x8..x15.
FAQ
Is c.addw just an assembler pseudo-instruction?
No. It is a 16-bit encoded instruction defined by the C extension.