Is the result zero-extended?
No. Bit 31 of the low 32-bit result is copied to bits 63..32: 0x80000000 becomes 0xffffffff80000000.
ADDW
RISC-V ADDW Instruction Details
Instruction ManualR-typeAdd lower 32 bits of rs1 and rs2, producing 32-bit result sign-extended to 64 bits
Instruction Syntax
addw rd, rs1, rs2
Operand Breakdown
rd: receives the low 32-bit sum sign-extended to 64 bits; x0 writes are discarded.
rs1 and rs2: provide low 32-bit values; overlapping names read the same old value.
RV64I only; no immediate and no full-width 64-bit addition.
RV64IArithmetic32-bit word operations
Instruction Behavior
ADDW (R-type, opcode=0111011, funct7=0000000, funct3=000) adds the lower 32 bits of rs1 and rs2, ignores overflow, sign-extends the 32-bit result to 64 bits, and writes it to rd. Unlike ADD in RV64I (a full 64-bit operation), ADDW operates only on the lower 32 bits and sign-extends.
ADDW Decode And Execute Animation
RV64I; XLEN=64; 32-bit result → sign extension
addw rd, rs1, rs2Execution Context
Assume successful instruction fetch, no asynchronous interrupt or extra extension checks; one initial value per register.
32-bit encoding
0x00C5853Bfunct7 [31..25]
0000000
rs2 [24..20]
01100 → x12
rs1 [19..15]
01011 → x11
funct3 [14..12]
000
rd [11..7]
01010 → x10
opcode [6..0]
0111011
x11=0x0000000000000014; x12=0x0000000000000009
Not computed
Fetch
Decode the current instruction fields and read sources before writeback; no result has been committed.
x10=0x0000000000000007; PC=0x0000000000002000
Current architectural state (before commit)
Current architectural state (before commit)
These are teaching steps for architectural effects, not processor pipeline stages or cycles.
Quick Understanding & Search Notes
Add lower 32 bits of rs1 and rs2, producing 32-bit result sign-extended to 64 bits
Result: rd=sext64((rs1[31:0]+rs2[31:0])[31:0]).
Writes to x0 are discarded; sources use their values before writeback.
Common Usage Scenarios
32-bit addition in RV64
RV64I, x11=0x7fffffff and x12=1: addw x10, x11, x12 yields 0xffffffff80000000.
Sign extension of a 32-bit result
RV64I, x11=0x7fffffff and x12=1: addw x10, x11, x12 yields 0xffffffff80000000.
Pre-Use Checklist
Syntax Check
- Register fields select x0–x31 or their ABI names.
- ADDW is RV64I-only; both sources are registers.
Semantic Check
- Ignore upper 32 source bits, retain the low 32-bit sum, then sign-extend bit 31 to 64 bits.
- Arithmetic overflow raises no exception; x0 writes are discarded, and overlapping registers are read before writeback.
Pitfalls / Common Confusions
RV64I only; unavailable in RV32I.
Ignore upper 32 input bits, keep the low 32-bit sum, and copy bit 31 to bits 63..32; this is not full-width 64-bit addition.
Arithmetic overflow raises no exception.