ADDW
RISC-V ADDW Instruction Details
Instruction ManualR-typeAdd lower 32 bits of rs1 and rs2, producing 32-bit result sign-extended to 64 bits
Instruction Syntax
addw rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
RV64IArithmetic32-bit Operational
Instruction Encoding
31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
ADDW uses opcode 0111011 (0x3b), funct3 000, funct7 0000000. The rs1 and rs2 fields select the two source registers, and rd selects the destination register.
Format: R-type
opcode: 0111011 (0x3b)
funct3: 000 (0x0)
funct7: 0000000 (0x00)
Instruction Behavior
ADDW (R-type, opcode=0111011, funct7=0000000, funct3=000) adds the lower 32 bits of rs1 and rs2, ignores overflow, sign-extends the 32-bit result to 64 bits, and writes it to rd. Unlike ADD (full 64-bit operation), ADDW operates only on the lower 32 bits and sign-extends.
Common Usage Scenarios
Address & Pointer
Understand this scenario with real code like «addw x10, x11, x12 # x10 = sign-extend((x11[31:0] + x12[31:0])[31:0])».
Basic Arithmetic
Understand this scenario with real code like «addw x10, x11, x12 # x10 = sign-extend((x11[31:0] + x12[31:0])[31:0])».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Overflow is silently ignored
Result is always 32-bit sign-extended
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
These W-suffix forms belong to RV64I or RV64 extension instructions; RV32 has no corresponding forms.