Is it available on RV32?
No. SRLIW, SRLW, and SUBW are RV64I word-operation forms.
SUBW
RISC-V SUBW Instruction Details
Instruction ManualR-typeSubtract lower 32 bits of rs2 from rs1, producing 32-bit result sign-extended to 64 bits
Instruction Syntax
subw rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
RV64IArithmetic32-bit Operational
Instruction Encoding
31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
SUBW uses opcode 0111011 (0x3b), funct3 000, funct7 0100000. The rs1 and rs2 fields select the two source registers, and rd selects the destination register.
Format: R-type
opcode: 0111011 (0x3b)
funct3: 000 (0x0)
funct7: 0100000 (0x20)
Instruction Behavior
SUBW (R-type, opcode=0111011, funct7=0100000, funct3=000) subtracts the lower 32 bits of rs2 from rs1, ignores overflow, sign-extends the 32-bit result to 64 bits, and writes it to rd. Unlike SUB (full 64-bit operation), SUBW operates only on the lower 32 bits.
Quick Understanding & Search Notes
SUBW is an RV64I W-suffix integer instruction: it uses the low 32 bits of its inputs, produces a 32-bit result, then sign-extends bit 31 to 64 bits.
The W suffix is not a normal 64-bit operation; the written value is always a sign-extended 32-bit result.
SUBW ignores overflow and writes the sign-extended low 32 bits of the difference.
Common Usage Scenarios
Basic Arithmetic
Understand this scenario with real code like «subw x10, x11, x12 # x10 = sign-extend((x11[31:0] - x12[31:0])[31:0])».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Overflow is silently ignored
Pay attention to operand order: rs2 subtracted from rs1
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
They exist in RV64/RV128-like environments, not RV32.
FAQ
Why can a logical shift still sign-extend?
The logical shift forms a 32-bit result first; the W-instruction rule then sign-extends bit 31 to 64 bits.