Is it available on RV32?
No. SRLIW, SRLW, and SUBW are RV64I word-operation forms.
SUBW
RISC-V SUBW Instruction Details
Instruction ManualR-typeSubtract lower 32 bits of rs2 from rs1, producing 32-bit result sign-extended to 64 bits
Instruction Syntax
subw rd, rs1, rs2
Operand Breakdown
rd: receives a 32-bit result sign-extended to 64 bits; x0 discards writes.
rs1: minuend; rs2: subtrahend. Keep the low 32-bit difference and ignore overflow.
RV64I-only, with no immediate operand; overlapping registers use source values before writeback.
RV64IArithmetic32-bit Operation
Instruction Behavior
SUBW (R-type, opcode=0111011, funct7=0100000, funct3=000) subtracts the lower 32 bits of rs2 from rs1, ignores overflow, sign-extends the 32-bit result to 64 bits, and writes it to rd. Unlike SUB on RV64 (full 64-bit operation), SUBW operates only on the lower 32 bits.
SUBW Decode And Execute Animation
RV64I; XLEN=64; 32-bit result → sign extension
subw rd, rs1, rs2Execution Context
Assume successful instruction fetch, no asynchronous interrupt or extra extension checks; one initial value per register.
32-bit encoding
0x40C5853Bfunct7 [31..25]
0100000
rs2 [24..20]
01100 → x12
rs1 [19..15]
01011 → x11
funct3 [14..12]
000
rd [11..7]
01010 → x10
opcode [6..0]
0111011
x11=0x0000000000000014; x12=0x0000000000000009
Not computed
Fetch
Decode the current instruction fields and read sources before writeback; no result has been committed.
x10=0x0000000000000007; PC=0x0000000000002000
Current architectural state (before commit)
Current architectural state (before commit)
These are teaching steps for architectural effects, not processor pipeline stages or cycles.
Quick Understanding & Search Notes
SUBW is an RV64I W-suffix integer instruction: it uses the low 32 bits of its inputs, produces a 32-bit result, then sign-extends bit 31 to 64 bits.
The W suffix is not a normal 64-bit operation; the written value is always a sign-extended 32-bit result.
SUBW ignores overflow and writes the sign-extended low 32 bits of the difference.
rd, rs1, and rs2 use full five-bit integer-register fields; x0 reads as zero and discards writes. Encodings with rd=x0 are HINTs designated for future standard use.
Common Usage Scenarios
Basic Arithmetic
RV64I, x11=0x80000000 and x12=1: subw x10, x11, x12 yields 0x000000007fffffff, ignoring overflow and sign-extending the low 32-bit difference.
Pre-Use Checklist
Syntax Check
- RV64I-only; rd, rs1 and rs2 are full five-bit GPR fields, with no rs3 or immediate.
Semantic Check
- Keep the low 32-bit rs1-rs2 difference, then sign-extend bit 31 to 64 bits; overflow is ignored.
- Overlapping sources use pre-writeback values; rd=x0 is a HINT designated for future standard use, leaving registers and memory unchanged.
Pitfalls / Common Confusions
Overflow is silently ignored
Pay attention to operand order: rs2 subtracted from rs1
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
SUBW is an RV64I instruction; RV32I has no W form of this instruction.
FAQ
What happens on SUBW overflow?
SUBW ignores overflow: it retains the low 32 bits of the difference, then sign-extends that 32-bit result to 64 bits.