Is it available on RV32?
No. SRLIW, SRLW, and SUBW are RV64I word-operation forms.
SUBW
RISC-V SUBW Instruction Details
Instruction ManualR-typeSubtract lower 32 bits of rs2 from rs1, producing 32-bit result sign-extended to 64 bits
Instruction Syntax
subw rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
RV64IArithmetic32-bit Operational
Instruction Behavior
SUBW (R-type, opcode=0111011, funct7=0100000, funct3=000) subtracts the lower 32 bits of rs2 from rs1, ignores overflow, sign-extends the 32-bit result to 64 bits, and writes it to rd. Unlike SUB (full 64-bit operation), SUBW operates only on the lower 32 bits.
SUBW Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
subw
,
,
Execution Context
t1(x6)
0x0000000000000014
t2(x7)
0x0000000000000007
31..25
24..20
19..15
14..12
11..7
6..0
0100000
funct7
00111
rs2
00110
rs1
000
funct3
00101
rd
0111011
opcode
Execution Data Path
instruction
0x407302BB
opcode
0111011 -> OP-32
funct3
000 -> SUBW
funct7
0100000 -> base ALU selector
rd / rs1 / rs2
t0(x5) / t1(x6) / t2(x7)
32-bit subtract
0x0000000000000014 - 0x0000000000000007 -> low 32 bits 0x0000000D -> sext.w 0x000000000000000D
x5
t0(x5) = 0x000000000000000D
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x407302BB
syntax : subw t0(x5), t1(x6), t2(x7)
result : t0(x5) = 0x000000000000000D
Architectural Result
t0(x5) = 0x000000000000000D
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SUBW is an RV64I W-suffix integer instruction: it uses the low 32 bits of its inputs, produces a 32-bit result, then sign-extends bit 31 to 64 bits.
The W suffix is not a normal 64-bit operation; the written value is always a sign-extended 32-bit result.
SUBW ignores overflow and writes the sign-extended low 32 bits of the difference.
Common Usage Scenarios
Basic Arithmetic
Understand this scenario with real code like «subw x10, x11, x12 # x10 = sign-extend((x11[31:0] - x12[31:0])[31:0])».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
Overflow is silently ignored
Pay attention to operand order: rs2 subtracted from rs1
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
SUBW is an RV64I instruction; RV32I has no W form of this instruction.
FAQ
What happens on SUBW overflow?
SUBW ignores overflow: it retains the low 32 bits of the difference, then sign-extends that 32-bit result to 64 bits.