RISC-V SLLIW Instruction Details
Instruction ManualI-typeShift 32-bit value in rs1 left logically by immediate, sign-extend 32-bit result to 64 bits
Instruction Syntax
Instruction Encoding
SLLIW uses opcode 0011011 (0x1b), funct3 001, funct7 0000000. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.
Instruction Behavior
SLLIW (I-type, opcode=0011011, funct3=001, funct7=0000000) performs a logical left shift on the lower 32 bits of rs1 by the shift amount encoded in imm[4:0], zeros are shifted into the lower bits. The 32-bit result is sign-extended to 64 bits. imm[5] must be 0, otherwise the encoding is reserved.
Common Usage Scenarios
Understand this scenario with real code like «slliw x10, x11, 3 # x10 = sign-extend((x11[31:0] << 3)[31:0])».
Understand this scenario with real code like «slliw x10, x11, 3 # x10 = sign-extend((x11[31:0] << 3)[31:0])».
Pre-Use Checklist
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.