RISC-V SLLIW Instruction Details
Instruction ManualI-typeShift 32-bit value in rs1 left logically by immediate, sign-extend 32-bit result to 64 bits
Instruction Syntax
Instruction Behavior
SLLIW is an I-type instruction with opcode=0011011, funct3=001, and imm[11:5]=0000000. It logically shifts the low 32 bits of rs1 by imm[4:0], fills low bits with zero, and sign-extends the 32-bit result to 64 bits in rd. Encodings with imm[5] equal to 1 are reserved.
SLLIW Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Common Usage Scenarios
Understand this scenario with real code like «slliw x10, x11, 3 # x10 = sign-extend((x11[31:0] << 3)[31:0])».
Understand this scenario with real code like «slliw x10, x11, 3 # x10 = sign-extend((x11[31:0] << 3)[31:0])».
Pre-Use Checklist
- Verify the immediate field is within the valid range.
- Confirm source register rs1 points to the correct operand.
- Check if the immediate sign-extension matches expectations.
- Ensure the result register rd has a clear purpose.