Why can a logical left shift produce all ones in the upper 32 bits?
The shift fills low bits with zero within 32 bits; the W form then sign-extends result bit 31 to 64 bits. When bit 31 is 1, the upper 32 bits are all ones.
SLLIW
RISC-V SLLIW Instruction Details
Instruction ManualI-typeShift 32-bit value in rs1 left logically by immediate, sign-extend 32-bit result to 64 bits
Instruction Syntax
slliw rd, rs1, shamt
Operand Breakdown
rd: selects x0–x31; writes to x0 are discarded. rs1: supplies the source value before writeback.
shamt: 0–31; imm[11:5] is fixed to 0000000, and encodings with imm[5]=1 are reserved.
RV64I-only; ignore upper 32 source bits, retain the low 32-bit shift result, then sign-extend to 64 bits.
RV64IArithmetic32-bit Shift
Instruction Behavior
SLLIW is an I-type instruction with opcode=0011011, funct3=001, and imm[11:5]=0000000. It logically shifts the low 32 bits of rs1 by imm[4:0], fills low bits with zero, and sign-extends the 32-bit result to 64 bits in rd. Encodings with imm[5] equal to 1 are reserved.
SLLIW Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
shamt
slliw
,
,
Execution Context
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
t1(x6)
0x0000000000000014
31..25
24..20
19..15
14..12
11..7
6..0
0000000
fixed imm[11:5]
00010
shamt[4:0]
00110
rs1
001
funct3
00101
rd
0011011
opcode
Execution Data Path
instruction
0x0023129B
opcode
0011011 -> OP-IMM-32
funct3
001 -> SLLIW
imm[11:5]
imm[11:5]=0000000 fixed; shamt[4:0]=00010
rd / rs1
t0(x5) / t1(x6)
imm[11:5] + shamt[4:0]
imm[11:5]=0000000 fixed; shamt[4:0]=00010
32-bit logical shift
Not computed
x5
t0(x5) = 0x0000000000003001; pc = 0x0000000000002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x0023129B
syntax : slliw t0(x5), t1(x6), 2
Pending result: Not computed
Current architectural state
t0(x5) = 0x0000000000003001; pc = 0x0000000000002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
Shift 32-bit value in rs1 left logically by immediate, sign-extend 32-bit result to 64 bits
RV64I-only; sign-extend the 32-bit left-shift result to 64 bits from bit 31.
Shift amount is 0–31: imm[4:0], with imm[11:5]=0000000; encodings with imm[5]=1 are reserved.
Common Usage Scenarios
32-bit logical left shift
RV64I, x11=0x40000000: slliw x10, x11, 1 gives 0xffffffff80000000; shifted bit 31 is 1, so the upper 32 bits are all ones.
Pre-Use Checklist
Syntax Check
- Register operands select x0–x31 or their ABI names; sources use values before writeback.
- SLLIW is RV64I-only; shamt is 0–31 with imm[11:5]=0000000, and encodings with imm[5]=1 are reserved.
Semantic Check
- Shift 32-bit value in rs1 left logically by immediate, sign-extend 32-bit result to 64 bits
- x0 is always zero and discards writes; integer computation raises no arithmetic exception.
Pitfalls / Common Confusions
SLLIW encodes shamt only in 0..31; SLLIW encodings with imm[5] not equal to 0 are reserved.
Result is sign-extended, upper 32 bits follow bit 31
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
These W-suffix forms belong to RV64I or RV64 extension instructions; RV32 has no corresponding forms.