RISC-V SLLW Instruction Details
Instruction ManualR-typeShift lower 32 bits of rs1 left logically by rs2[4:0], sign-extend 32-bit result to 64 bits
Instruction Syntax
Instruction Behavior
SLLW (R-type, opcode=0111011, funct7=0000000, funct3=001) performs a logical left shift on the lower 32 bits of rs1 by the shift amount in rs2[4:0]. Zeros are shifted into the lower bits. The 32-bit result is sign-extended to 64 bits.
SLLW Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Common Usage Scenarios
Understand this scenario with real code like «sllw x10, x11, x12 # x10 = sign-extend((x11[31:0] << x12[4:0])[31:0])».
Understand this scenario with real code like «sllw x10, x11, x12 # x10 = sign-extend((x11[31:0] << x12[4:0])[31:0])».
Pre-Use Checklist
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.