Why can a logical left shift produce all ones in the upper 32 bits?
The shift fills low bits with zero within 32 bits; the W form then sign-extends result bit 31 to 64 bits. When bit 31 is 1, the upper 32 bits are all ones.
SLLW
RISC-V SLLW Instruction Details
Instruction ManualR-typeShift lower 32 bits of rs1 left logically by rs2[4:0], sign-extend 32-bit result to 64 bits
Instruction Syntax
sllw rd, rs1, rs2
Operand Breakdown
rd: selects x0–x31; writes to x0 are discarded. rs1: supplies the source value before writeback.
rs2: only its low 5 bits supply the shift amount; it is not an immediate.
RV64I-only; ignore upper 32 source bits, retain the low 32-bit shift result, then sign-extend to 64 bits.
RV64IArithmetic32-bit Shift
Instruction Behavior
SLLW (R-type, opcode=0111011, funct7=0000000, funct3=001) performs a logical left shift on the lower 32 bits of rs1 by the shift amount in rs2[4:0]. Zeros are shifted into the lower bits. The 32-bit result is sign-extended to 64 bits.
SLLW Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
sllw
,
,
Execution Context
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
t1(x6)
0x0000000000000014
sp(x2)
0x0000000000000002
31..25
24..20
19..15
14..12
11..7
6..0
0000000
funct7
00010
rs2
00110
rs1
001
funct3
00101
rd
0111011
opcode
Execution Data Path
instruction
0x002312BB
opcode
0111011 -> OP-32
funct3
001 -> SLLW
funct7
0000000 -> base ALU op
rd / rs1 / rs2
t0(x5) / t1(x6) / sp(x2)
shamt
rs2[4:0]=00010 -> 2
32-bit logical shift
Not computed
x5
t0(x5) = 0x0000000000003001; pc = 0x0000000000002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x002312BB
syntax : sllw t0(x5), t1(x6), sp(x2)
Pending result: Not computed
Current architectural state
t0(x5) = 0x0000000000003001; pc = 0x0000000000002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
Shift lower 32 bits of rs1 left logically by rs2[4:0], sign-extend 32-bit result to 64 bits
RV64I-only; sign-extend the 32-bit left-shift result to 64 bits from bit 31.
Shift amount is 0–31: rs2[4:0]; other source high bits do not contribute to the amount.
Common Usage Scenarios
32-bit logical left shift
RV64I, x11=0x40000000 and x12=33: sllw x10, x11, x12 uses shift amount 1 and gives 0xffffffff80000000.
Pre-Use Checklist
Syntax Check
- Register operands select x0–x31 or their ABI names; sources use values before writeback.
- SLLW is RV64I-only; rd, rs1 and rs2 are register fields with no immediate operand.
Semantic Check
- Shift lower 32 bits of rs1 left logically by rs2[4:0], sign-extend 32-bit result to 64 bits
- x0 is always zero and discards writes; integer computation raises no arithmetic exception.
Pitfalls / Common Confusions
SLLW uses only rs2[4:0]; the remaining rs2 bits do not contribute to the shift amount.
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
These W-suffix forms belong to RV64I or RV64 extension instructions; RV32 has no corresponding forms.