Is the result zero-extended?
No. Bit 31 of the low 32-bit result is copied to bits 63..32: 0x80000000 becomes 0xffffffff80000000.
ADDIW
RISC-V ADDIW Instruction Details
Instruction ManualI-typeAdd a sign-extended 12-bit immediate to rs1, then sign-extend the low 32-bit result to 64 bits in rd.
Instruction Syntax
addiw rd, rs1, imm
Operand Breakdown
rd: receives the low 32-bit sum sign-extended to 64 bits; x0 writes are discarded.
rs1: source register whose upper 32 bits do not affect the result.
imm: signed 12-bit immediate from -2048 through 2047; RV64I only.
RV64IArithmetic32-bit word operations
Instruction Behavior
ADDIW (I-type, opcode=0011011, funct3=000) adds the sign-extended 12-bit immediate to rs1, ignores overflow, and writes the sign-extended low 32-bit result to rd. With an immediate of 0 it is the SEXT.W pseudoinstruction. Exists only in RV64I.
ADDIW Decode And Execute Animation
RV64I; XLEN=64; 32-bit result → sign extension
addiw rd, rs1, immExecution Context
Assume successful instruction fetch, no asynchronous interrupt or extra extension checks; one initial value per register.
32-bit encoding
0xFFF5851Bimm[11:0] [31..20]
111111111111
rs1 [19..15]
01011 → x11
funct3 [14..12]
000
rd [11..7]
01010 → x10
opcode [6..0]
0011011
x11=0x0000000000000014; imm=-1
Not computed
Fetch
Decode the current instruction fields and read sources before writeback; no result has been committed.
x10=0x0000000000000007; PC=0x0000000000002000
Current architectural state (before commit)
Current architectural state (before commit)
These are teaching steps for architectural effects, not processor pipeline stages or cycles.
Quick Understanding & Search Notes
Add a sign-extended 12-bit immediate to rs1, then sign-extend the low 32-bit result to 64 bits in rd.
Result: rd=sext64((rs1+immediate)[31:0]).
Writes to x0 are discarded; sources use their values before writeback.
Common Usage Scenarios
32-bit addition in RV64
RV64I, x11=0x7fffffff: addiw x10, x11, 1 yields 0xffffffff80000000; this is not 64-bit addition.
Sign extension of a 32-bit result
RV64I, x11=0x7fffffff: addiw x10, x11, 1 yields 0xffffffff80000000; this is not 64-bit addition.
Pre-Use Checklist
Syntax Check
- Register fields select x0–x31 or their ABI names.
- ADDIW is RV64I-only; its signed 12-bit immediate is exactly -2048 through 2047.
Semantic Check
- Ignore upper 32 source bits, retain the low 32-bit sum, then sign-extend bit 31 to 64 bits.
- Arithmetic overflow raises no exception; x0 writes are discarded, and overlapping registers are read before writeback.
Pitfalls / Common Confusions
RV64I only; unavailable in RV32I.
Ignore upper 32 input bits, keep the low 32-bit sum, and copy bit 31 to bits 63..32; this is not full-width 64-bit addition.
Arithmetic overflow raises no exception.
The immediate range is exactly -2048 through 2047, not symmetric ±2 KB.
FAQ
What does ADDIW with immediate zero do?
It sign-extends the low 32 bits of rs1 to 64 bits, equivalent to sext.w rd, rs1. It does not preserve arbitrary upper 32 bits of rs1.