RVOPcode
Home/Instructions/Add Immediate Word
ADDIW

RISC-V ADDIW Instruction Details

Instruction ManualI-type

Add a sign-extended 12-bit immediate to rs1, then sign-extend the low 32-bit result to 64 bits in rd.

Instruction Syntax

addiw rd, rs1, imm
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
RV64IArithmetic32-bit Operational
Related Search Terms
ADDIW instructionRISC-V ADDIWaddiw syntaxaddiw encodingaddiw I-type32-bit Operationaladdiw rv64 word

Instruction Encoding

31..20
imm[11:0]
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode

ADDIW uses opcode 0011011 (0x1b), funct3 000. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.

Format: I-type
opcode: 0011011 (0x1b)
funct3: 000 (0x0)

Instruction Behavior

ADDIW (I-type, opcode=0011011, funct3=000) adds the sign-extended 12-bit immediate to rs1, ignores overflow, and writes the sign-extended low 32-bit result to rd. With an immediate of 0 it is the SEXT.W pseudoinstruction. Exists only in RV64I.

Common Usage Scenarios

Address & Pointer

Understand this scenario with real code like «addiw x10, x11, 42 # x10 = sign-extend((x11 + 42)[31:0])».

Type Conversion

Understand this scenario with real code like «addiw x10, x11, 42 # x10 = sign-extend((x11 + 42)[31:0])».

RV64-Specific Operations

Understand this scenario with real code like «addiw x10, x11, 42 # x10 = sign-extend((x11 + 42)[31:0])».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is I-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Result is always 32-bit sign-extended, not suitable for 64-bit pointer arithmetic
Immediate range is only ±2KB
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
These W-suffix forms belong to RV64I or RV64 extension instructions; RV32 has no corresponding forms.