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ADDIW

RISC-V ADDIW Instruction Details

Instruction ManualI-type

Add a sign-extended 12-bit immediate to rs1, then sign-extend the low 32-bit result to 64 bits in rd.

Instruction Syntax

addiw rd, rs1, imm
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
RV64IArithmetic32-bit Operational
Related Search Terms
ADDIW instructionRISC-V ADDIWaddiw syntaxaddiw encodingaddiw I-type32-bit Operationaladdiw rv64 word

Instruction Behavior

ADDIW (I-type, opcode=0011011, funct3=000) adds the sign-extended 12-bit immediate to rs1, ignores overflow, and writes the sign-extended low 32-bit result to rd. With an immediate of 0 it is the SEXT.W pseudoinstruction. Exists only in RV64I.

ADDIW Decode And Execute Animation

Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.

rd
rs1
imm
addiw
,
,
Execution Context
t1(x6)
0x0000000000000014
31..20
19..15
14..12
11..7
6..0
111111111111
imm[11:0]
00110
rs1
000
funct3
00101
rd
0011011
opcode
Execution Data Path
instruction
0xFFF3029B
opcode
0011011 -> OP-IMM-32
funct3
000 -> ADDIW
rd / rs1
t0(x5) / t1(x6)
imm[11:0]
111111111111 -> sign_extend = 0xFFFFFFFFFFFFFFFF
32-bit add
0x0000000000000014 + 0xFFFFFFFFFFFFFFFF -> low 32 bits 0x00000013 -> sext.w 0x0000000000000013
x5
t0(x5) = 0x0000000000000013
Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0xFFF3029B
syntax : addiw t0(x5), t1(x6), -1
result : t0(x5) = 0x0000000000000013
Architectural Result
t0(x5) = 0x0000000000000013

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Common Usage Scenarios

Address & Pointer

Understand this scenario with real code like «addiw x10, x11, 42 # x10 = sign-extend((x11 + 42)[31:0])».

Type Conversion

Understand this scenario with real code like «addiw x10, x11, 42 # x10 = sign-extend((x11 + 42)[31:0])».

RV64-Specific Operations

Understand this scenario with real code like «addiw x10, x11, 42 # x10 = sign-extend((x11 + 42)[31:0])».

Pre-Use Checklist

Syntax Check
  • Verify the immediate field is within the valid range.
  • Confirm source register rs1 points to the correct operand.
Semantic Check
  • Check if the immediate sign-extension matches expectations.
  • Ensure the result register rd has a clear purpose.

Pitfalls / Common Confusions

Result is always 32-bit sign-extended, not suitable for 64-bit pointer arithmetic
Immediate range is only ±2KB
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
These W-suffix forms belong to RV64I or RV64 extension instructions; RV32 has no corresponding forms.