RVOPcode
Home/Instructions/C-SUBW
C.SUBW

RISC-V C.SUBW Instruction Details

Instruction ManualCA format

32-bit subtract with sign-extend to 64. CA format, RV64C.

Instruction Syntax

c.subw rd', rs2'
Operand Breakdown
This is a CA format-format instruction. Confirm operand positions based on the assembly syntax.
CCompressed Instruction
Related Search Terms
c.subw instructionc.subw syntaxRV64C c.subwc.subw sign extendc.subw rd rs2

Instruction Behavior

c.subw is an RV64C CA-format instruction. It subtracts rs2' from rd' as a 32-bit value, sign-extends bit 31 to XLEN, and writes rd'.

C.SUBW Decode & Execute Animation

Shows only manual-defined compressed fields, operands, and architectural state; it does not model a pipeline, cache, or timing.

Execution context (RV64)
x8 <- sext.w(0x0000000080000000 - 0x0000000000000001) = 0x000000007FFFFFFF
16-bit encoding fields
15..13
funct3
100
12
bit12
1
9..7
rd'/rs1'
000
6..5
funct2
00
4..2
rs2'
001
1..0
op
01
Current calculation

rd'/rs1'=x8 ; rs2'=x9

The commit step reveals the architectural result.

Quick Understanding & Search Notes

c.subw is an RV64C CA-format instruction. It subtracts rs2' from rd' as a 32-bit value, sign-extends bit 31 to XLEN, and writes rd'.

Compressed instructions usually mirror a 32-bit base instruction semantic, but with register-subset, immediate-encoding, or XLEN restrictions.
This W form is defined for RV64C, not RV32C.
Do not read the W suffix as a full-XLEN subtraction.
rd' and rs2' use the compressed register subset x8..x15.
RISC-V Unprivileged ISA Manual, C compressed extension

Common Usage Scenarios

Compressed & Code Size

Understand this scenario with real code like «c.subw x8, x9 # x8 = sext_w(x8-x9)».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is CA format.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

This W form is defined for RV64C, not RV32C.
Do not read the W suffix as a full-XLEN subtraction.
rd' and rs2' use the compressed register subset x8..x15.

FAQ

Why does c.subw have register restrictions?

Many C formats encode registers with shorter fields, so some forms can access only x8..x15 or fixed registers.

Is c.subw just an assembler pseudo-instruction?

No. It is a 16-bit encoded instruction defined by the C extension.