Why does c.subw have register restrictions?
Many C formats encode registers with shorter fields, so some forms can access only x8..x15 or fixed registers.
C.SUBW
RISC-V C.SUBW Instruction Details
Instruction ManualCA formatRV64C 16-bit CA subtraction: sign-extend the low 32 bits of rd'-rs2' to 64 bits and write rd'.
Instruction Syntax
c.subw rd', rs2'
RV64 C 2.0/Zca; 16-bit CA format, funct6=100111, funct2=00, op=01.
The three-bit rd'/rs1' and rs2' fields 000–111 select x8–x15; rd' is both an old-value source and the destination.
Take the low 32 bits of old x[rd']−old x[rs2'], then sign-extend bit31 to 64 bits and write rd'; identical sources share one old value. This encoding is reserved in RV32.
CCompressed Instruction
Related Search Terms
Instruction Behavior
c.subw is an RV64C CA-format instruction. It subtracts rs2' from rd' as a 32-bit value, sign-extends bit 31 to XLEN, and writes rd'.
C.SUBW Decode & Execute Animation
Shows only manual-defined compressed fields, operands, and architectural state; it does not model a pipeline, cache, or timing.
Execution context (RV64 C/Zca)
x8 <- sext.w(0x0000000080000000 - 0x0000000000000001) = 0x000000007FFFFFFF
16-bit encoding fields
15..10
funct6
100111
9..7
rd'/rs1'
000
6..5
funct2
00
4..2
rs2'
001
1..0
op
01
Current calculation
rd'/rs1'=000 -> x8; rs2'=001 -> x9
The commit step reveals the architectural result.
Quick Understanding & Search Notes
c.subw is an RV64C CA-format instruction. It subtracts rs2' from rd' as a 32-bit value, sign-extends bit 31 to XLEN, and writes rd'.
Compressed instructions usually mirror a 32-bit base instruction semantic, but with register-subset, immediate-encoding, or XLEN restrictions.
This W form is defined for RV64C, not RV32C.
Do not read the W suffix as a full-XLEN subtraction.
rd' and rs2' use the compressed register subset x8..x15.
Common Usage Scenarios
Compressed & Code Size
RV64 C/Zca, old x8=0 and x9=1: c.subw x8, x9 has low 32-bit difference 0xffffffff and writes sign-extended x8=0xffffffffffffffff.
Pre-Use Checklist
Syntax Check
- RV64 C 2.0/Zca; 16-bit CA format, funct6=100111, funct2=00, op=01.
- The three-bit rd'/rs1' and rs2' fields 000–111 select x8–x15; rd' is both an old-value source and the destination.
Semantic Check
- Take the low 32 bits of old x[rd']−old x[rs2'], then sign-extend bit31 to 64 bits and write rd'; identical sources share one old value. This encoding is reserved in RV32.
Pitfalls / Common Confusions
This W form is defined for RV64C, not RV32C.
Do not read the W suffix as a full-XLEN subtraction.
rd' and rs2' use the compressed register subset x8..x15.
FAQ
Is c.subw just an assembler pseudo-instruction?
No. It is a 16-bit encoded instruction defined by the C extension.