C.SUB

RISC-V C.SUB Instruction Details

Q: Is it always equivalent to a same-named 32-bit instruction?

Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.

Q: Why do register restrictions matter?

Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.

Instruction ManualC-type

Subtract rs2' from rd', write to rd'. CA format.

Instruction Syntax

c.sub rd', rs2'

Operand Breakdown

Compressed instructions are 16 bits; registers are often limited to x8–x15.

Immediate fields are narrower. Refer to the full encoding for this compressed instruction.

CCompressed Instruction

Related Search Terms

C.SUB instruction RISC-V C.SUB c.sub syntax c.sub encoding c.sub C c.sub compressed instruction compressed subtract

Instruction Behavior

C.SUB (CA format, x8-x15 only) computes subtraction of rd' and rs2', writes to rd'. Expands to sub rd',rd',rs2'.

C.SUB Decode & Execute Animation

Shows only official 16-bit fields, conditions, and architectural state; it does not model a pipeline, cache, or timing.

c.subrd',rs2'

Execution context

XLENx[rd'/x10]x[rs2'/x11]

x10 <- 0x0000FE1F

16-bit encoding fields

15..10

funct6

100011

9..7

rd'/rs1'

010

6..5

funct2

4..2

rs2'

011

1..0

Execution data path

CA fields restore rd'/rs1' to x10 and rs2' to x11; both three-bit fields map to x8-x15.

0x0000FF0F - 0x000000F0 = 0x0000FE1F (mod 2^32)

x10 <- 0x0000FE1F

Architectural state has not been committed.

Quick Understanding & Search Notes

C.SUB subtracts rs2' from rd' and writes rd'. Both CA compact-register fields select only x8-x15.

The CA rd'/rs1' and rs2' fields are three bits each and map to x8-x15.

C.SUB is an XLEN-bit subtraction, without an immediate or the RV64 word sign-extension semantics.

RISC-V Unprivileged ISA Manual, C Extension

Common Usage Scenarios

Basic Arithmetic

Understand this scenario with real code like «c.sub x8, x9 # x8 -= x9».

Pre-Use Checklist

Syntax Check

Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
Confirm rd/rs1'/rs2' fields map to x8–x15.

Semantic Check

Note the limited operand space of compressed instructions.
Verify this compressed instruction has a corresponding 32-bit expansion.

Pitfalls / Common Confusions

Only x8-x15 registers (CA format, 3-bit register fields)

There is no immediate operand; rd' is both the read left operand and the writeback destination

FAQ

Is it always equivalent to a same-named 32-bit instruction?