RVOPcode
Home/Instructions/C-ADDIW
C.ADDIW

RISC-V C.ADDIW Instruction Details

Instruction ManualC-type

Add sign-extended 6-bit imm to rd; 32-bit result sign-extended. CI format, RV64C.

Instruction Syntax

c.addiw rd, imm
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Related Search Terms
C.ADDIW instructionRISC-V C.ADDIWc.addiw syntaxc.addiw encodingc.addiw Cc.addiw compressed instructioncompressed ADDIW

Instruction Behavior

C.ADDIW (CI format, RV64 only) adds sign-extended 6-bit immediate to rd, sign-extends lower 32 bits to 64 bits. Expands to addiw rd,rd,imm. imm=0 is equivalent to sext.w rd. Valid only when rd≠x0.

Quick Understanding & Search Notes

C.ADDIW is the 16-bit encoding form for compressed ADDIW; its semantics and encodable register/immediate ranges must be read from the official C extension rules.

Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
RISC-V Unprivileged ISA Manual, C Extension

Common Usage Scenarios

Compressed & Code Size

Understand this scenario with real code like «c.addiw x10, 5 # x10 = sext_w(x10+5)».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is C-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

RV64C only
rd!=x0
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
They exist in RV64/RV128-like environments, not RV32.

FAQ

Is it always equivalent to a same-named 32-bit instruction?

Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.

Why do register restrictions matter?

Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.