Is immediate zero a no-op?
No. imm=0 still sign-extends the low 32 bits to 64. For example, 0x0000000080000000 becomes 0xFFFFFFFF80000000.
C.ADDIW
RISC-V C.ADDIW Instruction Details
Instruction ManualC-typeRV64 only: add a signed 6-bit immediate to rd, then sign-extend the low 32 bits to 64; rd=x0 is reserved.
Instruction Syntax
c.addiw rd, imm
Operand Breakdown
RV64 only, C 2.0 or Zca; 16-bit CI format.
Full five-bit rd/rs1 selects x1–x31 and imm is -32 through 31; rd=x0 is reserved.
Sign-extend the low 32 bits of rd+imm to 64; imm=0 is valid and sign-extends a word.
CCompressed Instruction
Instruction Behavior
C.ADDIW is a 16-bit CI instruction in C 2.0 / Zca, available only on RV64. rd is both source and destination and must be x1–x31; imm ranges from -32 through 31. Keep the low 32 bits of rd+imm and sign-extend bit 31 to 64 bits; overflow raises no arithmetic exception. It is equivalent to addiw rd, rd, imm. imm=0 is valid and performs sext.w rd, rd, rather than a HINT.
C.ADDIW Compressed Encoding Lab
Explore the 16-bit encoding, operands, calculation, and architectural result.
c.addiw,
RV64C / Zca, XLEN=64
XLEN
64 (RV64 only)
0x0000000080000000 + (-1), sext32 x10 <- 0x000000007FFFFFFF
16-bit encoding fields
15..13: funct3
001
12: imm[5]
1
11..7: rd/rs1
01010
6..2: imm[4:0]
11111
1..0: op
01
rd/rs1 = 01010 -> x10
imm[5|4:0] = 111111 -> sign-extended -1
0x0000000080000000 + (-1) -> low32 = 0x7FFFFFFF
sext32(0x7FFFFFFF) = 0x000000007FFFFFFF
Architectural state has not been committed.
Quick Understanding & Search Notes
RV64 only: add a signed 6-bit immediate to rd, then sign-extend the low 32 bits to 64; rd=x0 is reserved.
CI: funct3=001, op=01; imm[5] is bit 12, rd/rs1 is [11:7], and imm[4:0] is [6:2].
The same major encoding denotes C.JAL on RV32C; C.ADDIW applies only to RV64.
Common Usage Scenarios
Compressed & Code Size
RV64, x10=0x0000000080000000: c.addiw x10, -1 gives x10=0x000000007fffffff, sign-extending the low 32-bit sum.
Pre-Use Checklist
Syntax Check
- RV64 only, C 2.0 or Zca; 16-bit CI format.
- Full five-bit rd/rs1 selects x1–x31 and imm is -32 through 31; rd=x0 is reserved.
Semantic Check
- Sign-extend the low 32 bits of rd+imm to 64; imm=0 is valid and sign-extends a word.
Pitfalls / Common Confusions
RV64 only; rd=x0 is reserved.
imm is -32 through 31; imm=0 is valid and sign-extends a word.
Only the low 32 bits of the sum are kept, then sign-extended to 64 bits.
FAQ
Is rd=x0 a HINT?
No. C.ADDIW code points with rd=x0 are reserved. Valid rd values are x1–x31.