Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
C.ADDIW
RISC-V C.ADDIW Instruction Details
Instruction ManualC-typeAdd sign-extended 6-bit imm to rd; 32-bit result sign-extended. CI format, RV64C.
Instruction Syntax
c.addiw rd, imm
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Instruction Behavior
C.ADDIW (CI format, RV64 only) adds sign-extended 6-bit immediate to rd, sign-extends lower 32 bits to 64 bits. Expands to addiw rd,rd,imm. imm=0 is equivalent to sext.w rd. Valid only when rd≠x0.
C.ADDIW Decode & Execute Animation
Shows only official 16-bit decode, operands, computation, and architectural state; it does not simulate a pipeline, cache, or timing.
c.addiw,
Execution context
XLEN
64 (RV64C only)
16-bit encoding fields
15..13
funct3
001
12
imm[5]
1
11..7
rd/rs1
01010
6..2
imm[4:0]
11111
1..0
op
01
Execution data path
old x10 = 0x0000000080000000
low 32 bits of old + sext(imm) = 0x7FFFFFFF
sext.w = 0x000000007FFFFFFF
Architectural state has not been committed.
Quick Understanding & Search Notes
C.ADDIW is the 16-bit encoding form for compressed ADDIW; its semantics and encodable register/immediate ranges must be read from the official C extension rules.
Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
Common Usage Scenarios
Compressed & Code Size
Understand this scenario with real code like «c.addiw x10, 5 # x10 = sext_w(x10+5)».
Pre-Use Checklist
Syntax Check
- Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
- Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
- Note the limited operand space of compressed instructions.
- Verify this compressed instruction has a corresponding 32-bit expansion.
Pitfalls / Common Confusions
RV64C only
rd!=x0
W-suffix instructions produce a 32-bit result and sign-extend bit 31 to XLEN; do not treat them as ordinary 64-bit operations.
C.ADDIW is an RV64C-only encoding; it does not exist in RV32C.
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.