Why can rd not be sp?
rd=x2 selects C.ADDI16SP, whose fields encode a stack-pointer increment; the ordinary C.LUI upper-constant formula does not apply.
C.LUI
RISC-V C.LUI Instruction Details
Instruction ManualC-typeRV32/RV64 C/Zca, 16-bit CI: place the nonzero 6-bit field in bits 17:12, clear the low 12 bits, and sign-extend bit 17 to XLEN.
Instruction Syntax
c.lui rd, imm
Operand Breakdown
RV32/RV64 C/Zca; 16-bit CI format. Ordinary full five-bit rd selects x1–x31 except x2.
Interpret the nonzero six-bit field as signed -32–31, place it in bits 17:12, and zero the low 12 bits.
Sign-extend bit 17 to XLEN. With a nonzero field, rd=x0 is a HINT and rd=x2 selects C.ADDI16SP.
Zero-field encodings are reserved for ordinary C.LUI; Zcmop assigns the eight with rd=x1,x3,…,x15 to C.MOP.n.
CZcaCompressed Instruction
Instruction Behavior
Ordinary C.LUI uses the full five-bit rd field, selecting x1–x31 except x2. Interpret the nonzero six-bit field as signed -32–31, shift it left by 12, then sign-extend to XLEN; it corresponds to LUI. With a nonzero field, rd=x0 is a HINT and rd=x2 selects C.ADDI16SP, whose immediate layout differs and must not use the C.LUI calculation. Zero-field encodings are reserved; Zcmop uses the eight with rd=x1,x3,…,x15 for C.MOP.n.
C.LUI Decode & Execute Animation
Shows only official 16-bit fields, address/immediate calculation, and architectural state; it does not simulate a pipeline, cache, endianness implementation, or timing.
c.lui,
Execution context
RV32 / RV64 C / Zca
x10 -> 0x0000000000001000
16-bit encoding fields
15..13
funct3
011
12
nzimm[17]
0
11..7
rd
01010
6..2
nzimm[16:12]
00001
1..0
op
01
Execution data path
CI fields: nzimm=1; rd=01010 -> x10. inst[12|6:2] -> 000001 -> signed 1; <<12; sext(bit17)
sext(1 << 12) = 0x0000000000001000
Architectural state has not been committed.
Quick Understanding & Search Notes
RV32/RV64 C/Zca, 16-bit CI: place the nonzero 6-bit field in bits 17:12, clear the low 12 bits, and sign-extend bit 17 to XLEN.
CI: inst[12] supplies nzimm[17], inst[6:2] supplies nzimm[16:12], and the low 12 bits are zero.
Sign-extend from bit 17: field -32 yields 0xfffe0000 on RV32 or 0xfffffffffffe0000 on RV64.
Common Usage Scenarios
Upper constant generation
RV32/RV64 C/Zca: c.lui x10, 1 writes 0x1000 to x10, with zero low 12 bits; old x10 is not a source.
Pre-Use Checklist
Syntax Check
- RV32/RV64 C/Zca; 16-bit CI format. Ordinary full five-bit rd selects x1–x31 except x2.
- Interpret the nonzero six-bit field as signed -32–31, place it in bits 17:12, and zero the low 12 bits.
Semantic Check
- Sign-extend bit 17 to XLEN. With a nonzero field, rd=x0 is a HINT and rd=x2 selects C.ADDI16SP.
- Zero-field encodings are reserved for ordinary C.LUI; Zcmop assigns the eight with rd=x1,x3,…,x15 to C.MOP.n.
Pitfalls / Common Confusions
The ordinary form requires rd≠x0,x2 and a nonzero immediate field.
With rd=x2, the same six bits use the scattered C.ADDI16SP layout, not an upper immediate.
The eight zero-field encodings assigned by Zcmop are C.MOP.n, not ordinary C.LUI.
FAQ
Is a zero field always reserved?
It is reserved for ordinary C.LUI. With Zcmop, the eight corresponding odd rd=x1…x15 encodings become C.MOP.n, which does not write registers.