Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
C.LUI
RISC-V C.LUI Instruction Details
Instruction ManualC-typeLoad non-zero 6-bit imm to rd[17:12]; clear lower 12 bits; sign-extend. CI format.
Instruction Syntax
c.lui rd, imm
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Instruction Behavior
C.LUI (CI format) loads non-zero 6-bit immediate into bits 17:12 of rd, clears lower 12 bits, sign-extends bit 17. Expands to lui rd,imm. rd≠{x0,x2} and imm≠0. HINT when rd=x0. C.ADDI16SP when rd=x2.
C.LUI Decode & Execute Animation
Shows only official 16-bit fields, address/immediate calculation, and architectural state; it does not simulate a pipeline, cache, endianness implementation, or timing.
c.lui,
Execution context
x10 -> 0x0000000000001000
16-bit encoding fields
15..13
funct3
011
12
nzimm[17]
0
11..7
rd
01010
6..2
nzimm[16:12]
00001
1..0
op
01
Execution data path
CI fields: nzimm=1; rd=01010 -> x10.
sext(1 << 12) = 0x0000000000001000
mem[0x0000000000000001][63:0] = 0x0000000000001000
Architectural state has not been committed.
Quick Understanding & Search Notes
C.LUI is the 16-bit encoding form for compressed load upper immediate; its semantics and encodable register/immediate ranges must be read from the official C extension rules.
Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
Common Usage Scenarios
Immediates & Constants
Understand this scenario with real code like «c.lui x10, 1 # x10 = 0x00001000».
Pre-Use Checklist
Syntax Check
- Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
- Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
- Note the limited operand space of compressed instructions.
- Verify this compressed instruction has a corresponding 32-bit expansion.
Pitfalls / Common Confusions
imm must be non-zero
rd!=x2 (otherwise C.ADDI16SP)
With nzimm=0, ordinary C.LUI encodings are reserved; if Zcmop is implemented, the eight encodings with rd=x1, x3, ..., x15 are C.MOP.n.
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.