Is CBO.INVAL equivalent to a fence?
No. CMO/prefetch has cache-block semantics and is not a general memory-ordering substitute.
CBO.INVAL
RISC-V CBO.INVAL Instruction Details
Instruction ManualI-typecache-block invalidate (Zicbom).
Instruction Syntax
cbo.inval offset(base)
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
ZicbomCache & Sync
Instruction Behavior
CBO.INVAL is a Zicbom cache-block management instruction that performs an invalidate operation on the cache block containing the address in rs1; depending on CSR programming, lower-privilege execution may trap or perform a flush instead. rs1 need not be aligned to the cache-block size; on faults, the faulting virtual address is the value in rs1. The cache-block size is discovered from the execution environment and is not fixed at 64 bytes; the offset may be omitted, and if present must be 0.
CBO.INVAL Decode And Cache-Block Animation
Shows the official CMO/prefetch encoding, offset(base) operands, effective-address-to-cache-block selection, and ISA-visible effects.
offset
base
cbo.inval()
Execution Context
31..20
19..15
14..12
11..7
6..0
000000000000
cbo op
01011
rs1
010
funct3=CBO
00000
rd=x0
0001111
MISC-MEM
Cache-Block Data Path
instruction
0x0005A00F
opcode
0001111 -> MISC-MEM
operation
000000000000 -> CBO.INVAL
funct3
010 -> CBO
offset/base
0(a1(x11))
effective addr
0x0000000000001018 + 0x0000000000000000 = 0x0000000000001018
cache block
0x0000000000001000..0x000000000000103F
operation
invalidate the target cache-block copy
complete
cache-block management semantics complete
Current Step
Receive the 32-bit CBO.INVAL encoding
CBO.INVAL uses a 32-bit encoding; the animation starts by splitting the official fields.
encoding: 0x0005A00F
syntax : cbo.inval 0(a1(x11))
effect : invalidate the target cache-block copy
Cache-Block Selection View
base
0x0000000000001018
EA
0x0000000000001018
target block
0x0000000000001000..0x000000000000103F
The example cache-block size is 64 bytes only to show how the address selects a block; the real size is discovered from the execution environment and is not fixed at 64 bytes.
This animation shows only architectural semantics from the RISC-V CMO extension: the effective address selects a cache block, execution can be environment-controlled, and prefetch is an ignorable HINT; it does not model concrete cache state, cache-line size, bus transactions, timing, or performance.
Quick Understanding & Search Notes
CBO.INVAL is a CMO cache-block operation; it locates a cache block by effective address but is not an ordinary load/store.
For cbo.*, any explicit offset must be zero and the target is the cache block containing rs1.
CBO.INVAL/CLEAN/FLUSH executability is controlled by environment configuration.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «cbo.inval 0(a1)».
Cache & Hints
Understand this scenario with real code like «cbo.inval 0(a1)».
Device & IO
Understand this scenario with real code like «cbo.inval 0(a1)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The assembly offset operand may be omitted; if present, it must evaluate to zero.
rs1 need not be aligned to cache-block size; fault reporting uses the rs1 virtual address.
Execution permission is controlled by xenvcfg-related fields and privilege/virtualization state.
FAQ
Must the address for CBO.INVAL be cache-block aligned?
CBO instructions do not require rs1 to be aligned to cache-block size.