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CBO.INVAL

RISC-V CBO.INVAL Instruction Details

Instruction ManualI-type

cache-block invalidate (Zicbom).

Instruction Syntax

cbo.inval offset(base)
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
ZicbomCache & Sync
Related Search Terms
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Instruction Behavior

CBO.INVAL is a Zicbom cache-block management instruction that performs an invalidate operation on the cache block containing the address in rs1; depending on CSR programming, lower-privilege execution may trap or perform a flush instead. rs1 need not be aligned to the cache-block size; on faults, the faulting virtual address is the value in rs1. The cache-block size is discovered from the execution environment and is not fixed at 64 bytes; the offset may be omitted, and if present must be 0.

Quick Understanding & Search Notes

CBO.INVAL is a CMO cache-block operation; it locates a cache block by effective address but is not an ordinary load/store.

For cbo.*, any explicit offset must be zero and the target is the cache block containing rs1.
CBO.INVAL/CLEAN/FLUSH executability is controlled by environment configuration.
RISC-V Unprivileged ISA Manual: CMO cache-block operation extensions

Common Usage Scenarios

Atomic & Sync

Understand this scenario with real code like «cbo.inval 0(a1)».

Cache & Hints

Understand this scenario with real code like «cbo.inval 0(a1)».

Device & IO

Understand this scenario with real code like «cbo.inval 0(a1)».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is I-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

The assembly offset operand may be omitted; if present, it must evaluate to zero.
rs1 need not be aligned to cache-block size; fault reporting uses the rs1 virtual address.
Execution permission is controlled by xenvcfg-related fields and privilege/virtualization state.

FAQ

Is CBO.INVAL equivalent to a fence?

No. CMO/prefetch has cache-block semantics and is not a general memory-ordering substitute.

Must the address for CBO.INVAL be cache-block aligned?

CBO instructions do not require rs1 to be aligned to cache-block size.