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CBO.INVAL

RISC-V CBO.INVAL Instruction Details

Instruction ManualCBO MISC-MEM fixed fields

cache-block invalidate (Zicbom).

Instruction Syntax

cbo.inval offset(base)

base selects integer x0–x31; x0 gives address 0. Any explicit offset must be 0 and may be omitted; no destination register is written.

32-bit MISC-MEM: operation=000000000000, rs1=base, funct3=010, rd=00000, opcode=0001111.

RV32/RV64 Zicbom; CBIE and privilege/virtualization state control execution. Illegal, virtual, or store-class access/page/guest-page faults are possible. CMOs have no address-misaligned exception.

Invalidate deallocates copies; CSRs may require flush, and implementations may also substitute flush. Translation selects a physical cache block; the environment supplies its size. Management operations obey store PPO plus ordering before subsequent overlapping-address loads; FENCE classifies them as W/O.

ZicbomCache & Sync

Related Search Terms

cbo.inval instruction RISC-V cbo.inval cbo.inval syntax cbo.inval encoding cbo.inval cache-block invalidate cbo.inval CMO cbo.inval cache block

Instruction Behavior

CBO.INVAL is a Zicbom cache-block management instruction that performs an invalidate operation on the cache block containing the address in rs1; depending on CSR programming, lower-privilege execution may trap or perform a flush instead. rs1 need not be aligned to the cache-block size; on faults, the faulting virtual address is the value in rs1. The cache-block size is discovered from the execution environment and is not fixed at 64 bytes; the offset may be omitted, and if present must be 0. An implementation may also perform flush when the CSRs select invalidate.

CBO.INVAL Decode And Cache-Block Animation

Shows the official CMO/prefetch encoding, offset(base) operands, effective-address-to-cache-block selection, and ISA-visible effects.

offset

base

cbo.inval

(

)

Execution ContextXLENbase address valuecache-block sizeenvironment permission

31..20

19..15

14..12

11..7

6..0

000000000000

cbo op

01011

rs1

010

funct3=CBO

00000

rd=x0

0001111

MISC-MEM

Cache-Block Data Path

instruction

0x0005A00F

opcode

0001111 -> MISC-MEM

operation

000000000000 -> CBO.INVAL

funct3

010 -> CBO

offset/base

0(x11)

effective addr

0x0000000000001018 + 0x0000000000000000 = 0x0000000000001018

cache block

0x0000000000001000..0x000000000000103F

operation

invalidate the target cache-block copy

complete

cache-block management semantics complete

Current Step

Receive the 32-bit CBO.INVAL encoding

CBO.INVAL uses a 32-bit encoding; the animation starts by splitting the official fields.

encoding: 0x0005A00F

syntax : cbo.inval 0(x11)

effect : invalidate the target cache-block copy

Cache-Block Selection View

base

0x0000000000001018

target block

0x0000000000001000..0x000000000000103F

The example cache-block size is 64 bytes only to show how the address selects a block; the real size is discovered from the execution environment and is not fixed at 64 bytes. This demonstration assumes identical virtual and physical addresses for the selected block; base x0 gives address 0.

This animation shows only architectural semantics from the RISC-V CMO extension: the effective address is translated before a cache block is selected, CBO execution can be environment-controlled, and prefetch is an ignorable HINT; it does not model concrete cache state, physical mappings, cache-line size, bus transactions, timing, or performance.

Quick Understanding & Search Notes

CBO.INVAL is a CMO cache-block operation; it locates a cache block by effective address but is not an ordinary load/store.

For cbo.*, any explicit offset must be zero and the target is the cache block containing rs1.

CBO.INVAL/CLEAN/FLUSH executability is controlled by environment configuration.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture The RISC-V Instruction Set Manual, Volume II: Privileged Architecture

Common Usage Scenarios

Data visibility between non-coherent agents

cbo.inval 0(a1). Initialize the example source and enable the required extensions and state. Assume permitted access, identical virtual/physical addresses, and 64-byte cache blocks.

Pre-Use Checklist

Syntax Check

base selects integer x0–x31; x0 gives address 0. Any explicit offset must be 0 and may be omitted; no destination register is written.
32-bit MISC-MEM: operation=000000000000, rs1=base, funct3=010, rd=00000, opcode=0001111.

Semantic Check

RV32/RV64 Zicbom; CBIE and privilege/virtualization state control execution. Illegal, virtual, or store-class access/page/guest-page faults are possible. CMOs have no address-misaligned exception.
Invalidate deallocates copies; CSRs may require flush, and implementations may also substitute flush. Translation selects a physical cache block; the environment supplies its size. Management operations obey store PPO plus ordering before subsequent overlapping-address loads; FENCE classifies them as W/O.

Pitfalls / Common Confusions

The assembly offset operand may be omitted; if present, it must evaluate to zero.

rs1 need not be aligned to cache-block size; fault reporting uses the rs1 virtual address.

Execution permission is controlled by xenvcfg-related fields and privilege/virtualization state.

FAQ

Is CBO.INVAL equivalent to a fence?

No. CMO/prefetch has cache-block semantics and is not a general memory-ordering substitute.

Must the address for CBO.INVAL be cache-block aligned?

CBO instructions do not require rs1 to be aligned to cache-block size.