Does FENCE flush caches?
Its architectural semantics are ordering constraints, not a general cache flush.
FENCE
RISC-V FENCE Instruction Details
Instruction ManualI-typeOrder memory reads/writes and device I/O operations according to pred/succ sets.
Instruction Syntax
fence pred, succ
Operand Breakdown
pred/succ: select predecessor and successor operation sets; I/O and memory R/W bits are distinct.
FENCE.TSO is a specific FENCE encoding and has no ordinary register operands.
RV32ICache & Sync
Instruction Encoding
31..20
imm[11:0]
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
FENCE uses opcode 0001111 (0x0f), funct3 000. FENCE encodings use pred/succ and fm fields to describe ordering constraints, not an ordinary register-operation format.
Format: I-type
opcode: 0001111 (0x0f)
funct3: 000 (0x0)
Instruction Behavior
FENCE uses pred and succ fields to name predecessor and successor operation sets: I for device input, O for device output, R for memory reads, and W for memory writes. It constrains the ordering of memory and I/O operations made observable by the current hart to other harts or external devices; standard software should set reserved rd and rs1 fields to zero.
Quick Understanding & Search Notes
FENCE is not a cache flush. It establishes ordering constraints for this hart's memory and device I/O operations according to the pred/succ sets.
pred and succ list the predecessor and successor operation classes to be ordered.
I/O bits are for device input/output ordering, while R/W bits are for memory reads/writes.
Common Usage Scenarios
Memory Ordering
Understand this scenario with real code like «fence rw, rw # full memory barrier: prior reads+writes before subsequent reads+writes».
Device & IO
Understand this scenario with real code like «fence rw, rw # full memory barrier: prior reads+writes before subsequent reads+writes».
Concurrent Synchronization
Understand this scenario with real code like «fence rw, rw # full memory barrier: prior reads+writes before subsequent reads+writes».
Pre-Use Checklist
Syntax Check
- Verify pred/succ bits cover the I/O or R/W operation sets that need ordering.
- Confirm FENCE is an ordering constraint, not a general cache-flush instruction.
Semantic Check
- Confirm the need is an ordering constraint for the current hart's operations becoming visible.
- Confirm whether I/O bits are needed; FENCE.TSO does not order device I/O.
Pitfalls / Common Confusions
I/O and R/W in pred/succ are distinct categories; device synchronization should not use only RW.
FENCE does not order external events observed through non-memory signaling.
Reserved rd/rs1 fields should be zero for future compatibility.
FAQ
Does FENCE directly execute on other harts?
No. It constrains the order in which the current hart's relevant operations become observable to other observers.