Does FENCE flush caches?
No. Its architectural semantics are ordering constraints, not a general cache flush.
FENCE
RISC-V FENCE Instruction Details
Instruction ManualI-typeOrder the current hart's memory reads/writes and device I/O operations according to pred/succ sets.
Instruction Syntax
fence pred, succ
32-bit MISC-MEM fields: fm[31:28], pred[27:24], succ[23:20], rs1[19:15], funct3=000, rd[11:7], opcode=0001111; these are not an arithmetic immediate.
pred/succ select I=1000, O=0100, R=0010, W=0001 operation sets. Normal fm=0000; standard software must zero rs1/rd.
Orders the current hart's selected predecessor/successor operations as observed by other harts and external devices. An empty set establishes no ordering between operation pairs.
RV32I/RV64I; no general-register writeback. The EEI defines I/O versus R/W access classes. Other signaling observations and cache flushing are outside these ordering guarantees.
RV32I/RV64ICache & Sync
Instruction Behavior
FENCE uses pred and succ fields to name predecessor and successor operation sets: I for device input, O for device output, R for memory reads, and W for memory writes. It constrains the ordering of memory and I/O operations made observable by the current hart to other harts or external devices; standard software must set reserved rd and rs1 fields to zero.
FENCE Decode And Ordering Animation
Shows the FENCE opcode encoding, fm/pred/succ fields, and current-hart observable ordering constraints without modeling cache, bus, or pipeline behavior.
pred
succ
fence,
Execution Contextcurrent-hart observable orderingnot a cache flush
31..28
27..24
23..20
19..15
14..12
11..7
6..0
0000
fm
0011
pred
0011
succ
00000
rs1=x0
000
funct3
00000
rd=x0
0001111
MISC-MEM
instruction
0x0330000F
opcode
0001111 -> MISC-MEM/FENCE
fm
0000
pred
0011 -> RW
succ
0011 -> RW
reserved
rs1=x0, rd=x0, funct3=000
ordering
orders predecessor RW operations before successor RW operations are observed
complete
Awaiting ordering completion
This animation shows only FENCE/PAUSE architectural semantics defined by the RISC-V unprivileged ISA; it does not represent processor-specific pause duration, cache behavior, interconnect protocol, or execution cost.
Quick Understanding & Search Notes
FENCE is not a cache flush. It uses pred/succ bit sets to describe which predecessor operations must be observed before which successor operations.
pred and succ list the predecessor and successor operation classes to be ordered.
I/O bits are for device input/output ordering, while R/W bits are for memory reads/writes.
An empty pred or succ set establishes no ordering between the listed predecessor and successor operations; some such fm=0 encodings are HINTs.
Ordinary FENCE uses fm=0; FENCE.TSO uses a specific fm encoding.
rd and rs1 are reserved fields and must be zero in standard software.
The EEI classifies address accesses as device I/O or memory R/W. FENCE does not order external-device observations through other signaling mechanisms; a single-hart system may still need device I/O ordering.
Common Usage Scenarios
Memory Ordering
Understand this scenario with real code like «fence rw, rw # full memory barrier: prior reads+writes before subsequent reads+writes».
Device & IO
When the EEI classifies the device accesses as I/O, fence iorw, iorw covers predecessor/successor device and memory ordering; fence rw, rw excludes the device I/O classes.
Concurrent Synchronization
Understand this scenario with real code like «fence rw, rw # full memory barrier: prior reads+writes before subsequent reads+writes».
Pre-Use Checklist
Syntax Check
- Verify pred/succ bits cover the I/O or R/W operation sets that need ordering.
- Confirm FENCE is an ordering constraint, not a general cache-flush instruction.
Semantic Check
- Confirm the need is an ordering constraint for the current hart's operations becoming visible.
- Confirm whether I/O bits are needed; FENCE.TSO does not order device I/O.
Pitfalls / Common Confusions
I/O and R/W in pred/succ are distinct categories; device synchronization should not use only RW.
FENCE is an ordering constraint, not a general cache-flush or pipeline-flush instruction.
An empty pred or succ set establishes no ordering between the named predecessor and successor operations; some such fm=0 encodings are HINTs and cannot be relied on for ordering.
Standard software must zero the reserved rd/rs1 fields for future compatibility.
FAQ
Does fence rw,rw order device I/O?
No for I/O classes. Device input/output ordering requires the I or O bits as appropriate.
Does FENCE directly execute on other harts?
No. It constrains the order in which the current hart's relevant operations become observable to other observers.