Does FENCE.TSO order device I/O?
No. Its pred/succ sets include only R/W memory bits, not I/O bits.
FENCE.TSO
RISC-V FENCE.TSO Instruction Details
Instruction ManualI-typeA specific FENCE TSO encoding that orders memory R/W, excludes device I/O, and does not force non-AMO store-to-load ordering.
Instruction Syntax
fence.tso
32-bit MISC-MEM fields: fm[31:28], pred[27:24], succ[23:20], rs1[19:15], funct3=000, rd[11:7], opcode=0001111; these are not an arithmetic immediate.
No explicit operands. Full standard encoding 0x8330000F: fm=1000, pred=succ=0011, rs1=rd=x0.
Orders Load→Load, Load→Store, Store→Store; non-AMO Store→Load is not required, and I/O is excluded. May execute as stronger FENCE RW,RW.
RV32I/RV64I; no general-register writeback. The EEI defines I/O versus R/W access classes. Other signaling observations and cache flushing are outside these ordering guarantees.
RV32I/RV64ICache & Sync
Instruction Behavior
FENCE.TSO is a specific FENCE encoding (fm=1000, pred=RW, succ=RW). It orders memory R/W operations but does not include device I/O bits; compared with FENCE RW,RW, it does not require non-AMO predecessor stores before non-AMO successor loads. Implementations may execute it as the stronger FENCE RW,RW.
FENCE.TSO Decode And Ordering Animation
Shows the FENCE opcode encoding, fm/pred/succ fields, and current-hart observable ordering constraints without modeling cache, bus, or pipeline behavior.
no explicit operands
fence.tsofence.tso
Execution Contextcurrent-hart observable orderingnot a cache flush
31..28
27..24
23..20
19..15
14..12
11..7
6..0
1000
fm
0011
pred
0011
succ
00000
rs1=x0
000
funct3
00000
rd=x0
0001111
MISC-MEM
instruction
0x8330000F
opcode
0001111 -> MISC-MEM/FENCE
fm
1000 -> TSO
pred
0011 -> RW
succ
0011 -> RW
reserved
rs1=x0, rd=x0, funct3=000
ordering
orders Load→Load, Load→Store, Store→Store; excludes I/O and does not require non-AMO Store→Load
complete
Awaiting ordering completion
This animation shows only FENCE/PAUSE architectural semantics defined by the RISC-V unprivileged ISA; it does not represent processor-specific pause duration, cache behavior, interconnect protocol, or execution cost.
Quick Understanding & Search Notes
FENCE.TSO is a specific TSO FENCE encoding: it covers only memory R/W, not device I/O, and allows non-AMO predecessor stores not to be ordered before non-AMO successor loads.
fm=1000 with pred=RW and succ=RW is the FENCE.TSO encoding.
FENCE.TSO has no I/O bits and cannot replace a FENCE that includes I/O ordering.
Compared with FENCE RW,RW, it does not require non-AMO store-to-load ordering.
An implementation may execute FENCE.TSO as the stronger FENCE RW,RW.
Specifically orders Load→Load, Load→Store, and Store→Store; non-AMO Store→Load is not required. This exception does not relax AMO ordering rules.
The complete standard encoding is 0x8330000F. It has no explicit operands and no general-register reads or writes.
Common Usage Scenarios
Memory Ordering
Understand this scenario with real code like «fence.tso # TSO-style memory ordering for R/W accesses».
Concurrent Synchronization
Understand this scenario with real code like «fence.tso # TSO-style memory ordering for R/W accesses».
Pre-Use Checklist
Syntax Check
- Verify this is the no-explicit-operand FENCE.TSO encoding.
- Verify the need is R/W memory ordering, not I/O ordering or cache flushing.
Semantic Check
- Confirm the need is an ordering constraint for the current hart's operations becoming visible.
- Confirm whether I/O bits are needed; FENCE.TSO does not order device I/O.
Pitfalls / Common Confusions
FENCE.TSO does not order device I/O; use a FENCE with I/O bits when I/O ordering is required.
FENCE.TSO is weaker than FENCE RW,RW because it does not force non-AMO store-to-load ordering.
Implementations may execute it as the stronger FENCE RW,RW, so do not assume it is always cheaper.
FAQ
Is FENCE.TSO as strong as fence rw,rw?
Architecturally it is weaker because it does not require non-AMO predecessor stores before non-AMO successor loads, although an implementation may execute it as the stronger fence rw,rw.