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PAUSE

RISC-V PAUSE Instruction Details

Instruction ManualI-type

Zihintpause bounded pause hint indicating the current hart retirement rate may be temporarily reduced or paused.

Instruction Syntax

pause
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
ZihintpauseMicroarch Hints
Related Search Terms
PAUSE instructionRISC-V PAUSEZihintpausepause encodingspin wait hintspin-wait loopFENCE hint

Instruction Behavior

PAUSE is a HINT defined by Zihintpause and encoded as a FENCE form with pred=W, succ=0, fm=0, rd=x0, and rs1=x0. It indicates that the current hart may be in a spin-wait sequence and that the instruction retirement rate may be temporarily reduced or paused; the effect duration must be bounded and may be zero. Because the successor set is empty, PAUSE mandates no memory ordering.

PAUSE Decode And Ordering Animation

Shows the FENCE opcode encoding, fm/pred/succ fields, and current-hart observable ordering constraints without modeling cache, bus, or pipeline behavior.

no explicit operands
pausepause
Execution Contextcurrent-hart observable orderingbounded hint, may be zero
31..28
27..24
23..20
19..15
14..12
11..7
6..0
0000
fm
0001
pred
0000
succ
00000
rs1=x0
000
funct3
00000
rd=x0
0001111
MISC-MEM
instruction
0x0100000F
opcode
0001111 -> MISC-MEM/FENCE
fm
0000
pred
0001 -> W
succ
0000 -> empty
reserved
rs1=x0, rd=x0, funct3=000
ordering
spin-wait hint; empty succ set mandates no memory ordering
complete
bounded hint complete

This animation shows only FENCE/PAUSE architectural semantics defined by the RISC-V unprivileged ISA; it does not represent processor-specific pause duration, cache behavior, interconnect protocol, or execution cost.

Quick Understanding & Search Notes

PAUSE is a FENCE-form spin-wait hint. It may let an implementation reduce or pause the current hart retirement rate for a bounded duration, but succ=0 means it mandates no memory ordering.

PAUSE is encoded as a FENCE form with fm=0, pred=W, succ=0, rs1=x0, and rd=x0.
The empty successor set means PAUSE mandates no memory ordering.
The pause effect must be bounded, and the duration may be zero.
PAUSE is for spin-wait loops, not a synchronization primitive or fixed-delay instruction.
RISC-V Unprivileged ISA Manual: Zihintpause PAUSE hint

Common Usage Scenarios

Atomic & Sync

Understand this scenario with real code like «pause # hint for spinlock busy-wait loop».

Concurrency & Multi-core

Understand this scenario with real code like «pause # hint for spinlock busy-wait loop».

Power Optimization

Understand this scenario with real code like «pause # hint for spinlock busy-wait loop».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is I-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

PAUSE is a performance/energy hint and does not guarantee a specific pause duration, power-saving effect, or scheduling effect.
PAUSE provides no memory ordering; it cannot replace FENCE, atomics, or lock protocols.
The official recommendation for portable spin-wait loops is generally to use one PAUSE before re-evaluating the loop condition.
Like other FENCE instructions, PAUSE cannot be used inside LR/SC sequences without voiding the forward-progress guarantee.

FAQ

Does PAUSE guarantee a fixed delay?

No. The official rule only requires the effect to be bounded, and the duration may be zero.

Can PAUSE replace FENCE?

No. PAUSE has an empty successor set and mandates no memory ordering.

Is PAUSE just a NOP?

It is a HINT; an implementation may reduce or pause the current hart retirement rate, but the duration may also be zero.