Does PAUSE guarantee a fixed delay?
No. The official rule only requires the effect to be bounded, and the duration may be zero.
PAUSE
RISC-V PAUSE Instruction Details
Instruction ManualI-typeZihintpause bounded pause hint indicating the current hart retirement rate may be temporarily reduced or paused.
Instruction Syntax
pause
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
ZihintpauseMicroarch Hints
Instruction Encoding
31..20
imm[11:0]
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
PAUSE uses opcode 0001111 (0x0f), funct3 000. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.
Format: I-type
opcode: 0001111 (0x0f)
funct3: 000 (0x0)
Instruction Behavior
PAUSE is a HINT defined by Zihintpause and encoded as a FENCE form with pred=W, succ=0, fm=0, rd=x0, and rs1=x0. It indicates that the current hart may be in a spin-wait sequence and that the instruction retirement rate may be temporarily reduced or paused; the effect duration must be bounded and may be zero. Because the successor set is empty, PAUSE mandates no memory ordering.
Quick Understanding & Search Notes
PAUSE tells the implementation the current hart may be spin-waiting; it may reduce or pause retirement, but the effect must be bounded and may be zero.
PAUSE is encoded in the FENCE opcode, but the empty successor set means it mandates no memory ordering.
It is intended for spin-wait loops, not as a general delay instruction or synchronization primitive.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «pause # hint for spinlock busy-wait loop».
Concurrency & Multi-core
Understand this scenario with real code like «pause # hint for spinlock busy-wait loop».
Power Optimization
Understand this scenario with real code like «pause # hint for spinlock busy-wait loop».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
PAUSE is a performance/energy hint and does not guarantee a specific pause duration, power-saving effect, or scheduling effect.
PAUSE provides no memory ordering; it cannot replace FENCE, atomics, or lock protocols.
The official recommendation for portable spin-wait loops is generally to use one PAUSE before re-evaluating the loop condition.
Like other FENCE instructions, PAUSE cannot be used inside LR/SC sequences without voiding the forward-progress guarantee.
FAQ
Can PAUSE replace FENCE?
No. PAUSE mandates no memory ordering.