Can WRS.STO replace LR/SC?
No. It waits on a reservation set; LR/SC, AMO, or CAS updates shared state.
WRS.STO
RISC-V WRS.STO Instruction Details
Instruction ManualI-typeWait on reservation set with short timeout
Instruction Syntax
wrs.sto
Operand Breakdown
WRS.STO has no explicit assembly operands; it uses a fixed SYSTEM I-type encoding.
funct12 is fixed to 000000011101, with rs1=x0, funct3=000, rd=x0, and opcode=1110011.
Reservation-set validity, pending interrupts, and the implementation-defined stall duration are implicit architectural or implementation state, not assembly register or immediate operands.
ZawrsCache & Sync
Instruction Encoding
31..20
funct12
19..15
rs1=x0
14..12
funct3
11..7
rd=x0
6..0
opcode
WRS-STO uses opcode 1110011 (0x73), funct3 000, funct12 000000011101, rs2 fixed x0. This fixed SYSTEM encoding has no explicit assembly register or immediate operand; funct12, rs1, funct3, rd, and opcode must match the constants listed in the manual.
Format: SYSTEM I-type fields
opcode: 1110011 (0x73)
funct3: 000 (0x0)
funct12: 000000011101 (0x01d)
rs2: fixed x0
Instruction Behavior
May temporarily stall a hart while its LR-established reservation set is valid, no pending interrupt is observed, and an implementation-defined short timeout has not elapsed. A timeout, store to the reservation set, interrupt, or implementation-selected end can resume execution.
Quick Understanding & Search Notes
WRS.STO is a Zawrs wait-on-reservation-set instruction: a hart can temporarily stall while its reservation set is valid, no pending interrupt is observed, and the short timeout has not elapsed; LR establishes that reservation set.
To wait for target bytes to be written, LR should first establish a reservation set containing them; the instruction has no address operand.
WRS.STO bounds the stall by an implementation-defined short timeout.
The instructions are available in all privilege modes, but WRS.NTO is affected by the mstatus.TW rule.
Common Usage Scenarios
Cache & Hints
Understand this scenario with real code like «retry: lr.w x10, (x11) ; ... ; wrs.sto ; j retry».
Device & IO
Understand this scenario with real code like «retry: lr.w x10, (x11) ; ... ; wrs.sto ; j retry».
Pre-Use Checklist
Syntax Check
- Verify the immediate field is within the valid range.
- Confirm source register rs1 points to the correct operand.
Semantic Check
- Check if the immediate sign-extension matches expectations.
- Ensure the result register rd has a clear purpose.
Pitfalls / Common Confusions
To wait for a memory location to be written, first use LR to establish a reservation set that includes its bytes.
The short-timeout duration is implementation-defined and must not be documented as a fixed cycle count.
Returning from the wait does not mean the condition is satisfied; software must reload and test the shared state.
FAQ
Will WRS.STO always sleep until memory changes?
No. An implementation may end the stall for any reason; software must re-check the condition.