LR.W
RISC-V LR.W Instruction Details
Instruction ManualR-typeLoad 32-bit word from address in rs1 and register a reservation for subsequent SC.W
Instruction Syntax
lr.w rd, (rs1)
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
AZalrscAtomic
Related Search Terms
Instruction Behavior
LR.W loads a word from the address in rs1, places the sign-extended value in rd, and registers a reservation set covering the addressed bytes. The reservation is used by subsequent SC.W for conditional store. Supports aq/rl bits for memory ordering. Value is sign-extended to 64 bits in RV64.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «lr.w.aq t0, (a0) # load word from *a0 with acquire ordering, set reservation».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Address must be 4-byte aligned
Must pair with SC.W
Stores from other harts invalidate reservation
New LR on same hart overwrites previous reservation