Is LR.W just LW with a marker?
No. LR.W and LW both read a 32-bit word and sign-extend it into rd, but LR.W also creates a reservation set that a later SC.W uses for its conditional store.
LR.W
RISC-V LR.W Instruction Details
Instruction ManualR-typeAtomically load a 32-bit word and create a reservation for a later SC.W conditional store
Instruction Syntax
lr.w rd, (rs1)
Operand Breakdown
rd: receives old memory, sign-extended to XLEN for LR.W; rd=x0 discards only writeback and does not cancel the access or reservation.
rs1: supplies the naturally aligned address directly, with no offset immediate; LR.W requires 4-byte alignment, and RV64-only LR.D requires 8-byte alignment.
Encoded rs2 is fixed to 00000, not a second source operand; funct5=00010, with independent aq/rl ordering bits.
AZalrscAtomic
Instruction Behavior
LR.W atomically reads a 32-bit word from the address in rs1, sign-extends the loaded value to XLEN, writes rd, and creates a reservation set covering the accessed bytes. It does not write memory; a later SC.W uses the reservation to decide whether its conditional store succeeds. aq can provide acquire semantics for an LR/SC sequence; setting rl on LR without aq is not guaranteed to provide stronger ordering, and ordering applies only to the address domain accessed by the instruction.
LR.W Atomic Decode And Execute Animation
Shows A / Zalrsc word atomic field decode, aq/rl ordering bits, a memory read, and reservation state update.
rd
rs1
lr.w,()
Execution Context
31..27
26
25
24..20
19..15
14..12
11..7
6..0
00010
funct5
1
aq
0
rl
00000
rs2=00000
01010
rs1
010
funct3
00101
rd
0101111
opcode
Atomic Data Path
instruction
0x140522AF
opcode
0101111 -> AMO
funct3
010 -> word width
funct5
00010 -> LR.W
aq / rl
1/0 -> acquire
rd / rs1
t0(x5) / a0(x10)=0x00001000
memory read
mem[0x00001000] -> old word 0x00000005
reservation
Not computed
rd / reservation
t0(x5) = unspecified initial value; mem[0x00001000] = 0x00000005
Current Step
Concept Step: receive the 32-bit atomic instruction encoding
A / Zalrsc-extension word atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.
encoding: 0x140522AF
syntax : lr.w.aq t0(x5), (a0(x10))
Pending result : Not computed
Assumes an aligned, readable LR/SC-capable region and successful fetch/access. The reservation contains all accessed bytes; its full implementation-defined size, interference from other harts/devices and SC success conditions are not modeled. aq/rl orders only the accessed memory/I/O domain. Steps are a teaching sequence.
Quick Understanding & Search Notes
LR.W is the first step in an LR/SC sequence: it reads the old 32-bit memory value and creates a reservation. The key idea is not an ordinary load, but “read old value + create reservation + let a later SC.W consume that reservation.”
The R-type rs2 field must be x0; funct5=00010, funct3=010, and opcode=0101111 identify LR.W.
LR.W reads a 32-bit word and sign-extends it to XLEN when writing rd; on RV64, high bits come from sign extension of bit 31.
LR.W creates a reservation set, but it does not guarantee that a later SC.W will succeed; software must still handle SC.W failure in a loop.
aq can provide acquire semantics for an LR/SC sequence; rl on LR without aq is not guaranteed to provide stronger ordering, and these bits do not change the basic data result: load the old value and create a reservation.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «lr.w.aq t0, (a0) # load word from *a0 with acquire ordering, set reservation».
Pre-Use Checklist
Syntax Check
- Syntax is rd, (rs1), with encoded rs2=00000 and independent aq/rl ordering bits.
Semantic Check
- Confirm Zalrsc or A support, a reservable region and natural alignment; LR.D is RV64-only. Misaligned LR raises address-misaligned or access-fault.
- Load old memory and reserve all accessed bytes; LR.W sign-extends to XLEN. Memory is not written, and later SC success is not guaranteed.
Pitfalls / Common Confusions
Address must be 4-byte aligned
LR.W only loads and reserves; a later SC.W attempts the conditional store
An observed store from another hart to the reservation set between LR.W and SC.W makes SC.W fail
New LR on same hart overwrites previous reservation
FAQ
Does SC.W always succeed after LR.W?
No. The reservation may be invalidated, and SC.W may fail; software should check the value written by SC.W to rd and retry the LR/SC sequence on failure.