Is LR.W just LW with a marker?
No. LR.W and LW both read a 32-bit word and sign-extend it into rd, but LR.W also creates a reservation set that a later SC.W uses for its conditional store.
LR.W
RISC-V LR.W Instruction Details
Instruction ManualR-typeAtomically load a 32-bit word and create a reservation for a later SC.W conditional store
Instruction Syntax
lr.w rd, (rs1)
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
AZalrscAtomic
Instruction Behavior
LR.W atomically reads a 32-bit word from the address in rs1, sign-extends the loaded value to XLEN, writes rd, and creates a reservation set covering the accessed bytes. It does not write memory; a later SC.W uses the reservation to decide whether its conditional store succeeds. The aq/rl bits provide memory-ordering constraints only for the address domain accessed by the instruction.
LR.W Atomic Decode And Execute Animation
Shows A-extension word atomic field decode, aq/rl ordering bits, memory read, and RMW state update.
rd
rs1
lr.w,()
Execution Context
31..27
26
25
24..20
19..15
14..12
11..7
6..0
00010
funct5
1
aq
0
rl
00000
rs2=00000
01010
rs1
010
funct3
00101
rd
0101111
opcode
Atomic Data Path
instruction
0x140522AF
opcode
0101111 -> AMO
funct3
010 -> word width
funct5
00010 -> LR.W
aq / rl
1/0 -> acquire
rd / rs1
t0(x5) / a0(x10)=0x00001000
memory read
mem[0x00001000] -> old word 0x00000005
reservation
create reservation for 4 bytes at 0x00001000
rd / reservation
t0(x5) = 0x00000005; reservation set created
Current Step
Concept Step: receive the 32-bit atomic instruction encoding
A-extension word atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.
encoding: 0x140522AF
syntax : lr.w t0(x5), (a0(x10))
result : t0(x5) = 0x00000005; reservation set created
This animation shows ISA-visible atomic read-modify-write, compare-and-swap, LR/SC reservation state, and ordering bits, not any specific CPU cache-coherence implementation, pipeline, or timing.
Quick Understanding & Search Notes
LR.W is the first step in an LR/SC sequence: it reads the old 32-bit memory value and creates a reservation. The key idea is not an ordinary load, but “read old value + create reservation + let a later SC.W consume that reservation.”
The R-type rs2 field must be x0; funct5=00010, funct3=010, and opcode=0101111 identify LR.W.
LR.W reads a 32-bit word and sign-extends it to XLEN when writing rd; on RV64, high bits come from sign extension of bit 31.
LR.W creates a reservation set, but it does not guarantee that a later SC.W will succeed; software must still handle SC.W failure in a loop.
The aq/rl bits affect memory ordering and do not change the basic data result: load the old value and create a reservation.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «lr.w.aq t0, (a0) # load word from *a0 with acquire ordering, set reservation».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Address must be 4-byte aligned
Must pair with SC.W
Stores from other harts invalidate reservation
New LR on same hart overwrites previous reservation
FAQ
Does SC.W always succeed after LR.W?
No. The reservation may be invalidated, and SC.W may fail; software should check the value written by SC.W to rd and retry the LR/SC sequence on failure.