AMOSWAP.W
RISC-V AMOSWAP.W Instruction Details
Instruction ManualR-typeAtomically swap 32-bit word: rd = *rs1, *rs1 = rs2
Instruction Syntax
amoswap.w rd, rs2, (rs1)
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
AZaamoAtomic
Instruction Behavior
AMOSWAP.W atomically loads the 32-bit value from the address in rs1 into rd (sign-extended), then stores the value from rs2 to the same address. Supports aq/rl bits for memory ordering (acquire/release/sequentially-consistent). Loaded value is sign-extended to 64 bits in RV64.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «amoswap.w.aq t0, t1, (a0) # atomic swap *a0 with t1, old value in t0».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Address must be 4-byte aligned
Not available for byte/halfword operations
AMO.W atomically accesses a 32-bit word; on RV64, the old value loaded into rd is sign-extended to XLEN.
AMO.W exists in RV32 and RV64 A/Zaamo environments; it is not RV64-only.