AMOSWAP.W

RISC-V AMOSWAP.W Instruction Details

Instruction ManualR-type

Atomically swap a 32-bit word: read the old memory value into rd and write the low 32 bits of rs2 back to the same address

Instruction Syntax

amoswap.w rd, rs2, (rs1)

Operand Breakdown

Destination rd: register receiving the operation result.

Source rs1: register holding the first operand.

Source rs2: register holding the second operand.

AZaamoAtomic

Related Search Terms

AMOSWAP.W instruction RISC-V AMOSWAP.W amoswap.w syntax amoswap.w encoding atomic swap word AMOSWAP.W aq rl RISC-V AMO swap

Instruction Behavior

AMOSWAP.W performs an atomic read-modify-write on the 32-bit word addressed by rs1: it reads the old memory value, sign-extends it into rd, and writes the low 32 bits of rs2 back to the same address. It does not use an LR/SC reservation; the aq/rl bits only affect ordering of this atomic memory operation relative to other memory operations in the same address domain.

AMOSWAP.W Atomic Decode And Execute Animation

Shows A-extension word atomic field decode, aq/rl ordering bits, memory read, and RMW state update.

rs2

rs1

amoswap.w

)

Execution ContextXLENmemory addressold memory wordrs2 wordaqrl

31..27

24..20

19..15

14..12

11..7

6..0

00001

funct5

01011

rs2

01010

rs1

010

funct3

00101

0101111

opcode

Atomic Data Path

instruction

0x0CB522AF

opcode

0101111 -> AMO

funct3

010 -> word width

funct5

00001 -> AMOSWAP.W

aq / rl

1/0 -> acquire

rd / rs2 / rs1

t0(x5) / a1(x11)=0x0000007F / a0(x10)=0x00001000

memory read

mem[0x00001000] -> old word 0x80000002

RMW

new memory word = rs2 word 0x0000007F

rd / memory

t0(x5) = 0x80000002; mem[0x00001000] = 0x0000007F

Current Step

Concept Step: receive the 32-bit atomic instruction encoding

A-extension word atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.

encoding: 0x0CB522AF

syntax : amoswap.w t0(x5), a1(x11), (a0(x10))

result : t0(x5) = 0x80000002; mem[0x00001000] = 0x0000007F

32-bit Word Result View

write

This animation shows ISA-visible atomic read-modify-write, compare-and-swap, LR/SC reservation state, and ordering bits, not any specific CPU cache-coherence implementation, pipeline, or timing.

Quick Understanding & Search Notes

AMOSWAP.W writes the pre-swap old memory value to rd, while memory receives the low 32 bits of rs2. It is a single AMO read-modify-write operation, not an LR/SC loop.

funct5=00001, funct3=010, and opcode=0101111 identify AMOSWAP.W; the aq/rl bits live in the high atomic-instruction field.

rd receives the old memory value sign-extended from the word result to XLEN; the low 32 bits of rs2 become the new memory word.

The AMO read and write form one atomic read-modify-write operation; the page animation shows only ISA-visible state changes.

On RV64, the old word written to rd is sign-extended, while the memory write remains a 32-bit word.

RISC-V Unprivileged ISA Manual: A Extension for Atomic Instructions

Common Usage Scenarios

Atomic & Sync

Understand this scenario with real code like «amoswap.w.aq t0, t1, (a0) # atomic swap *a0 with t1, old value in t0».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is R-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Address must be 4-byte aligned

Not available for byte/halfword operations

AMO.W atomically accesses a 32-bit word; on RV64, the old value loaded into rd is sign-extended to XLEN.

AMO.W exists in RV32 and RV64 A/Zaamo environments; it is not RV64-only.

FAQ

Does AMOSWAP.W write the new value or old value to rd?

rd receives the old 32-bit value from memory before the swap, sign-extended to XLEN. The low 32 bits of rs2 are the new value written to memory.

Does AMOSWAP.W require a preceding LR.W?

No. AMOSWAP.W is an independent AMO read-modify-write instruction and does not depend on an LR/SC reservation.