AMOSWAP.W

RISC-V AMOSWAP.W Instruction Details

Instruction ManualR-type

Atomically swap a 32-bit word: read the old memory value into rd and write the low 32 bits of rs2 back to the same address

Instruction Syntax

amoswap.w rd, rs2, (rs1)

Operand Breakdown

rd: receives old memory on a successful access; AMO.W sign-extends to XLEN on RV64, and rd=x0 discards register writeback.

rs1: supplies the address; use natural alignment or satisfy the misaligned atomicity granule PMA condition, in a region supporting this AMO.

rs2: uses its pre-execution value to compute new memory; AMO.W uses only the low 32 bits, while AMO.D uses all 64 bits.

funct5 selects the operation and funct3 the width; aq/rl are separate ordering bits, with no offset immediate or rs3.

AZaamoAtomic

Related Search Terms

AMOSWAP.W instruction RISC-V AMOSWAP.W amoswap.w syntax amoswap.w encoding atomic swap word AMOSWAP.W aq rl RISC-V AMO swap

Instruction Behavior

AMOSWAP.W performs an atomic read-modify-write on the 32-bit word addressed by rs1: it reads the old memory value, sign-extends it into rd, and writes the low 32 bits of rs2 back to the same address. It does not use an LR/SC reservation; the aq/rl bits only affect ordering of this atomic memory operation relative to other memory operations in the same address domain.

AMOSWAP.W Atomic Decode And Execute Animation

Shows A / Zaamo word atomic field decode, aq/rl ordering bits, a memory read, and RMW state update.

rs2

rs1

amoswap.w

)

Execution ContextXLENmemory addressold memory wordrs2 (32-bit register)aqrlPMA is present and all accessed bytes are in one misaligned atomicity granule

31..27

24..20

19..15

14..12

11..7

6..0

00001

funct5

01011

rs2

01010

rs1

010

funct3

00101

0101111

opcode

Atomic Data Path

instruction

0x0CB522AF

opcode

0101111 -> AMO

funct3

010 -> word width

funct5

00001 -> AMOSWAP.W

aq / rl

1/0 -> acquire

rd / rs2 / rs1

t0(x5) / a1(x11)[31:0]=0x0000007F / a0(x10)=0x00001000

memory read

mem[0x00001000] -> old word 0x80000002

RMW

Not computed

rd / memory

t0(x5) = unspecified initial value; mem[0x00001000] = 0x80000002

Current Step

Concept Step: receive the 32-bit atomic instruction encoding

A / Zaamo-extension word atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.

encoding: 0x0CB522AF

syntax : amoswap.w.aq t0(x5), a1(x11), (a0(x10))

Pending result : Not computed

32-bit Word Result View

write

Assumes the region supports this AMO and the access succeeds. Shows the operation, old-value return, memory update and aq/rl ordering in the accessed domain. Steps are a teaching sequence; access faults, CPU cache coherence, pipelines and timing are not modeled.

Quick Understanding & Search Notes

AMOSWAP.W writes the pre-swap old memory value to rd, while memory receives the low 32 bits of rs2. It is a single AMO read-modify-write operation, not an LR/SC loop.

funct5=00001, funct3=010, and opcode=0101111 identify AMOSWAP.W; the aq/rl bits live in the high atomic-instruction field.

rd receives the old memory value sign-extended from the word result to XLEN; the low 32 bits of rs2 become the new memory word.

The AMO read and write form one atomic read-modify-write operation; the page animation shows only ISA-visible state changes.

On RV64, the old word written to rd is sign-extended, while the memory write remains a 32-bit word.

rs2 uses its pre-execution value; rd=x0 discards the register writeback while the memory update still occurs.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Version 20260120: Official Release The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version 20260120: Official Release

Common Usage Scenarios

Atomic & Sync

Successful 32-bit access example: a2=0x1000, old memory=5, a1=3; amoswap.w a0, a1, (a2) returns a0=5 and updates memory to 3. The address is naturally aligned and the region supports this AMO.

Pre-Use Checklist

Syntax Check

rd, rs2, and rs1 select x0–x31 or their ABI names; syntax is rd, rs2, (rs1), with no rs3 or offset immediate.
Check funct5 for the operation and funct3 for access width; aq/rl are separate ordering bits, not a fixed funct7 constant.

Semantic Check

Check natural alignment or the misaligned atomicity granule PMA condition; the target region must support this AMO width and operation.
On success, rd receives old memory and the computed result goes to memory; rd=x0 discards only register writeback. On RV64, AMO.W sign-extends the old word and uses only rs2[31:0].

Pitfalls / Common Confusions

Normally requires a 4-byte naturally aligned address; a misaligned atomicity granule PMA avoids an address-alignment exception only when all accessed bytes lie within one granule.

AMOSWAP.W accesses a 32-bit word, rather than a byte or halfword.

AMO.W atomically accesses a 32-bit word; on RV64, the old value loaded into rd is sign-extended to XLEN.

AMO.W exists in RV32 and RV64 A/Zaamo environments; it is not RV64-only.

FAQ

Does AMOSWAP.W write the new value or old value to rd?

rd receives the old 32-bit value from memory before the swap, sign-extended to XLEN. The low 32 bits of rs2 are the new value written to memory.

Does AMOSWAP.W require a preceding LR.W?

No. AMOSWAP.W is an independent AMO read-modify-write instruction and does not depend on an LR/SC reservation.