AMOOR.W
RISC-V AMOOR.W Instruction Details
Instruction ManualR-typeAtomically OR 32-bit word: rd = *rs1, *rs1 |= rs2
Instruction Syntax
amoor.w rd, rs2, (rs1)
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
AZaamoAtomic
Instruction Behavior
AMOOR.W atomically loads the 32-bit value from the address in rs1 into rd (sign-extended), ORs it with rs2, and stores the result back. Supports aq/rl bits. Commonly used for atomic bit setting.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «amoor.w a0, a1, (a2) # a0 = *a2; *a2 |= a1».
Bit Operations & Masks
Understand this scenario with real code like «amoor.w a0, a1, (a2) # a0 = *a2; *a2 |= a1».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Returns old value before OR
AMO.W atomically accesses a 32-bit word; on RV64, the old value loaded into rd is sign-extended to XLEN.
AMO.W exists in RV32 and RV64 A/Zaamo environments; it is not RV64-only.