AMOOR.W

RISC-V AMOOR.W Instruction Details

Instruction ManualR-type

Atomic 32-bit word bitwise OR: rd returns the old memory word, while memory receives the 32-bit result of oldWord | rs2LowWord

Instruction Syntax

amoor.w rd, rs2, (rs1)

Operand Breakdown

rd: receives the old memory value read atomically; for AMOCAS, its pre-execution value also supplies the compare value.

rs1: directly supplies the atomic-memory address; AMO assembly syntax has no offset immediate field.

rs2: supplies the AMO source data; for AMOCAS, it is the swap value stored when the comparison matches.

AMO-type is this site's presentation label for the AMO-specific R-type field layout: funct5, aq, rl, rs2, rs1, funct3, rd, and the AMO opcode encode the operation.

AZaamoAtomic

Related Search Terms

AMOOR.W instruction RISC-V AMOOR.W amoor.w syntax amoor.w encoding atomic bitwise OR word AMOOR.W old value RISC-V AMO bitwise OR

Instruction Behavior

The following semantics assume the target region supports this AMO width and operation and the access succeeds. AMOOR.W performs an atomic read-modify-write on the 32-bit word addressed by rs1: it first reads the old memory word and sign-extends it into rd, then bitwise-ORs the old word with the low 32 bits of rs2. The resulting 32-bit word is written back to the same address. aq/rl add ordering only in the accessed memory or I/O address domain and do not change the bitwise-OR data result; ordering across both domains still needs FENCE. rs2 uses its pre-execution value; rd=x0 discards only the old-value register writeback, while the memory operation still occurs.

AMOOR.W Atomic Decode And Execute Animation

Shows A / Zaamo word atomic field decode, aq/rl ordering bits, a memory read, and RMW state update.

rs2

rs1

amoor.w

)

Execution ContextXLENmemory addressold memory wordrs2 (32-bit register)aqrlPMA is present and all accessed bytes are in one misaligned atomicity granule

31..27

24..20

19..15

14..12

11..7

6..0

01000

funct5

01011

rs2

01010

rs1

010

funct3

00101

0101111

opcode

Atomic Data Path

instruction

0x40B522AF

opcode

0101111 -> AMO

funct3

010 -> word width

funct5

01000 -> AMOOR.W

aq / rl

0/0 -> unordered

rd / rs2 / rs1

t0(x5) / a1(x11)[31:0]=0x0000FFF0 / a0(x10)=0x00001000

memory read

mem[0x00001000] -> old word 0xF000000F

RMW

0xF000000F | 0x0000FFF0 -> 0xF000FFFF

rd / memory

t0(x5) = 0xF000000F; mem[0x00001000] = 0xF000FFFF

Current Step

Concept Step: receive the 32-bit atomic instruction encoding

A / Zaamo-extension word atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.

encoding: 0x40B522AF

syntax : amoor.w t0(x5), a1(x11), (a0(x10))

result : t0(x5) = 0xF000000F; mem[0x00001000] = 0xF000FFFF

32-bit Word Result View

Assumes the region supports this AMO and the access succeeds. Shows the operation, old-value return, memory update and aq/rl ordering in the accessed domain. Steps are a teaching sequence; access faults, CPU cache coherence, pipelines and timing are not modeled.

Quick Understanding & Search Notes

AMOOR.W is used for atomic bit setting or flag merging. The value returned in rd on successful access with rd≠x0 is the old memory word; the new 32-bit word after the bitwise OR operation is written only to memory.

funct5=01000, funct3=010, and opcode=0101111 identify AMOOR.W; aq/rl bits do not change the data calculation.

rd receives the old memory word before the operation; memory receives the 32-bit result of oldWord | rs2LowWord.

AMO.W is a word-width AMO and normally requires a 4-byte naturally aligned address. On RV64, the old word in rd is sign-extended to XLEN; a misaligned atomicity granule PMA avoids an address-alignment exception when all accessed bytes lie in one granule.

AMOOR.W is a bitwise word operation; each result bit comes from the same bit position of the old word and rs2 low word.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Version 20260120 — §§13.1, 13.4; Chapter 36 The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version 20260120 — §§3.6.3.1, 3.6.4

Common Usage Scenarios

Atomic & Sync

Successful 32-bit access example: a2=0x1000, old memory=5, a1=3; amoor.w a0, a1, (a2) returns a0=5 and updates memory to 7. The address is naturally aligned and the region supports this AMO.

Bit Operations & Masks

Successful 32-bit access example: a2=0x1000, old memory=5, a1=3; amoor.w a0, a1, (a2) returns a0=5 and updates memory to 7. The address is naturally aligned and the region supports this AMO.

Pre-Use Checklist

Syntax Check

rd, rs2, and rs1 select x0–x31 or their ABI names; syntax is rd, rs2, (rs1), with no rs3 or offset immediate.
Check funct5 for the operation and funct3 for access width; aq/rl are separate ordering bits, not a fixed funct7 constant.

Semantic Check

Check natural alignment or the misaligned atomicity granule PMA condition; the target region must support this AMO width and operation.
On success, rd receives old memory and the computed result goes to memory; rd=x0 discards only register writeback. On RV64, AMO.W sign-extends the old word and uses only rs2[31:0].

Pitfalls / Common Confusions

rd holds the old memory word before the operation, not the new bitwise OR memory result.

AMO.W atomically accesses a 32-bit word; on RV64, the old word loaded into rd is sign-extended to XLEN.

Only the low 32-bit word of rs2 participates in the calculation, and memory receives a 32-bit word result.

aq/rl constrain memory ordering only; they do not change the value of oldWord | rs2LowWord.

FAQ

Does AMOOR.W place the new memory result in rd?

No. AMOOR.W places the old memory word before the operation in rd; the result of oldWord | rs2LowWord is written back to memory.

Do aq/rl bits change the bitwise OR result of AMOOR.W?

No. aq/rl only affect memory-ordering constraints; they do not change this AMO.W instruction's 32-bit data result.