Does AMOXOR.W place the new memory result in rd?
No. AMOXOR.W places the old memory word before the operation in rd; the result of oldWord ^ rs2LowWord is written back to memory.
AMOXOR.W
RISC-V AMOXOR.W Instruction Details
Instruction ManualR-typeAtomic 32-bit word bitwise XOR: rd returns the old memory word, while memory receives the 32-bit result of oldWord ^ rs2LowWord
Instruction Syntax
amoxor.w rd, rs2, (rs1)
Operand Breakdown
rd: receives old memory on a successful access; AMO.W sign-extends to XLEN on RV64, and rd=x0 discards register writeback.
rs1: supplies the address; use natural alignment or satisfy the misaligned atomicity granule PMA condition, in a region supporting this AMO.
rs2: uses its pre-execution value to compute new memory; AMO.W uses only the low 32 bits, while AMO.D uses all 64 bits.
funct5 selects the operation and funct3 the width; aq/rl are separate ordering bits, with no offset immediate or rs3.
AZaamoAtomic
Instruction Behavior
AMOXOR.W performs an atomic read-modify-write on the 32-bit word addressed by rs1: it returns the sign-extended old memory word in rd and bitwise-XORs the old word with the low 32 bits of the pre-execution rs2 value. The resulting 32-bit word is written back to the same address. aq/rl bits affect memory ordering only; they do not change the bitwise XOR data result.
AMOXOR.W Atomic Decode And Execute Animation
Shows A / Zaamo word atomic field decode, aq/rl ordering bits, a memory read, and RMW state update.
rd
rs2
rs1
amoxor.w,,()
Execution Context
31..27
26
25
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11..7
6..0
00100
funct5
0
aq
0
rl
01011
rs2
01010
rs1
010
funct3
00101
rd
0101111
opcode
Atomic Data Path
instruction
0x20B522AF
opcode
0101111 -> AMO
funct3
010 -> word width
funct5
00100 -> AMOXOR.W
aq / rl
0/0 -> unordered
rd / rs2 / rs1
t0(x5) / a1(x11)[31:0]=0x0F0F0F0F / a0(x10)=0x00001000
memory read
mem[0x00001000] -> old word 0xAAAAAAAA
RMW
Not computed
rd / memory
t0(x5) = unspecified initial value; mem[0x00001000] = 0xAAAAAAAA
Current Step
Concept Step: receive the 32-bit atomic instruction encoding
A / Zaamo-extension word atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.
encoding: 0x20B522AF
syntax : amoxor.w t0(x5), a1(x11), (a0(x10))
Pending result : Not computed
32-bit Word Result View
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rs2 word
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Assumes the region supports this AMO and the access succeeds. Shows the operation, old-value return, memory update and aq/rl ordering in the accessed domain. Steps are a teaching sequence; access faults, CPU cache coherence, pipelines and timing are not modeled.
Quick Understanding & Search Notes
AMOXOR.W is used for atomic bit toggling. On successful access with rd≠x0, rd receives the old memory word; the new 32-bit word after the bitwise XOR operation is written only to memory.
funct5=00100, funct3=010, and opcode=0101111 identify AMOXOR.W; aq/rl bits do not change the data calculation.
rd receives the old memory word before the operation; memory receives the 32-bit result of oldWord ^ rs2LowWord.
AMO.W is a word-width AMO; on RV64, the old word in rd is sign-extended to XLEN.
AMOXOR.W is a bitwise word operation; each result bit comes from the same bit position of the old word and rs2 low word.
AMO.W normally requires a 4-byte naturally aligned address; a misaligned atomicity granule PMA avoids an address-alignment exception only when all accessed bytes lie within one granule.
rs2 uses its pre-execution value; rd=x0 discards the register writeback while the memory update still occurs.
Common Usage Scenarios
Atomic & Sync
Successful 32-bit access example: a2=0x1000, old memory=5, a1=3; amoxor.w a0, a1, (a2) returns a0=5 and updates memory to 6. The address is naturally aligned and the region supports this AMO.
Atomic Bit Toggling
Successful 32-bit access example: a2=0x1000, old memory=5, a1=3; amoxor.w a0, a1, (a2) returns a0=5 and updates memory to 6. The address is naturally aligned and the region supports this AMO.
Pre-Use Checklist
Syntax Check
- rd, rs2, and rs1 select x0–x31 or their ABI names; syntax is rd, rs2, (rs1), with no rs3 or offset immediate.
- Check funct5 for the operation and funct3 for access width; aq/rl are separate ordering bits, not a fixed funct7 constant.
Semantic Check
- Check natural alignment or the misaligned atomicity granule PMA condition; the target region must support this AMO width and operation.
- On success, rd receives old memory and the computed result goes to memory; rd=x0 discards only register writeback. On RV64, AMO.W sign-extends the old word and uses only rs2[31:0].
Pitfalls / Common Confusions
rd holds the old memory word before the operation, not the new bitwise XOR memory result.
AMO.W atomically accesses a 32-bit word; on RV64, the old word loaded into rd is sign-extended to XLEN.
Only the low 32-bit word of rs2 participates in the calculation, and memory receives a 32-bit word result.
aq/rl constrain memory ordering only; they do not change the value of oldWord ^ rs2LowWord.
Normally requires a 4-byte naturally aligned address; a misaligned atomicity granule PMA avoids an address-alignment exception only when all accessed bytes lie within one granule.
FAQ
Do aq/rl bits change the bitwise XOR result of AMOXOR.W?
No. aq/rl only affect memory-ordering constraints; they do not change this AMO.W instruction's 32-bit data result.