Does AMOXOR.D place the new memory result in rd?
No. AMOXOR.D places the old 64-bit memory value before the operation in rd; the result of oldDoubleword ^ rs2Doubleword is written back to memory.
AMOXOR.D
RISC-V AMOXOR.D Instruction Details
Instruction ManualR-typeRV64 atomic 64-bit doubleword XOR: rd returns the old memory value, while memory receives oldDoubleword ^ rs2Doubleword
Instruction Syntax
amoxor.d rd, rs2, (rs1)
Operand Breakdown
rd: receives old memory on a successful access; AMO.W sign-extends to XLEN on RV64, and rd=x0 discards register writeback.
rs1: supplies the address; use natural alignment or satisfy the misaligned atomicity granule PMA condition, in a region supporting this AMO.
rs2: uses its pre-execution value to compute new memory; AMO.W uses only the low 32 bits, while AMO.D uses all 64 bits.
funct5 selects the operation and funct3 the width; aq/rl are separate ordering bits, with no offset immediate or rs3.
AZaamoAtomic Operation
Instruction Behavior
AMOXOR.D performs an atomic read-modify-write on the 64-bit doubleword addressed by rs1: it returns the old memory doubleword in rd and, using the pre-execution rs2 value, computes oldDoubleword ^ rs2Doubleword using XOR semantics and writes the 64-bit result back to the same address. The operation uses matching bit positions from the old doubleword and the rs2 doubleword. aq/rl bits affect memory ordering only; they do not change the data result.
AMOXOR.D Atomic Decode And Execute Animation
Shows A / Zaamo doubleword atomic field decode, aq/rl ordering bits, a memory read, and RMW state update.
rd
rs2
rs1
amoxor.d,,()
Execution Context
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00100
funct5
0
aq
0
rl
01011
rs2
01010
rs1
011
funct3
00101
rd
0101111
opcode
Atomic Data Path
instruction
0x20B532AF
opcode
0101111 -> AMO
funct3
011 -> doubleword width
funct5
00100 -> AMOXOR.D
aq / rl
0/0 -> unordered
rd / rs2 / rs1
t0(x5) / a1(x11)=0x0F0F0F0F0F0F0F0F / a0(x10)=0x0000000000001000
memory read
mem[0x0000000000001000] -> old doubleword 0xAAAAAAAAAAAAAAAA
RMW
Not computed
rd / memory
t0(x5) = unspecified initial value; mem[0x0000000000001000] = 0xAAAAAAAAAAAAAAAA
Current Step
Concept Step: receive the 32-bit atomic instruction encoding
A / Zaamo-extension doubleword atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.
encoding: 0x20B532AF
syntax : amoxor.d t0(x5), a1(x11), (a0(x10))
Pending result : Not computed
64-bit Doubleword Result View
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rs2 doubleword
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Assumes the region supports this AMO and the access succeeds. Shows the operation, old-value return, memory update and aq/rl ordering in the accessed domain. Steps are a teaching sequence; access faults, CPU cache coherence, pipelines and timing are not modeled.
Quick Understanding & Search Notes
AMOXOR.D is an RV64 64-bit AMO.D read-modify-write instruction. On successful access with rd≠x0, rd returns the old doubleword before the operation; only the result of oldDoubleword ^ rs2Doubleword is written back to memory, so keep old-value return separate from memory update.
funct5=00100, funct3=011, and opcode=0101111 identify AMOXOR.D; aq/rl bits do not change the data calculation.
rd receives the old 64-bit memory doubleword before the operation; memory receives the 64-bit result computed by this AMO.D instruction.
AMOXOR.D is an RV64-only doubleword AMO and normally requires an 8-byte naturally aligned address; a misaligned atomicity granule PMA avoids an address-alignment exception only when all accessed bytes lie within one granule.
AMOXOR.D is a 64-bit bitwise logical AMO; each result bit comes from the same bit position of the old doubleword and the rs2 doubleword.
rs2 uses its pre-execution value; rd=x0 discards the register writeback while the memory update still occurs.
Common Usage Scenarios
Atomic & Sync
Successful 64-bit access example: a2=0x1000, old memory=5, a1=3; amoxor.d a0, a1, (a2) returns a0=5 and updates memory to 6. The address is naturally aligned and the region supports this AMO.
Atomic Bit Toggling
Successful 64-bit access example: a2=0x1000, old memory=5, a1=3; amoxor.d a0, a1, (a2) returns a0=5 and updates memory to 6. The address is naturally aligned and the region supports this AMO.
Pre-Use Checklist
Syntax Check
- rd, rs2, and rs1 select x0–x31 or their ABI names; syntax is rd, rs2, (rs1), with no rs3 or offset immediate.
- Check funct5 for the operation and funct3 for access width; aq/rl are separate ordering bits, not a fixed funct7 constant.
Semantic Check
- Check natural alignment or the misaligned atomicity granule PMA condition; the target region must support this AMO width and operation.
- On success, rd receives old memory and the computed result goes to memory; rd=x0 discards only register writeback. On RV64, AMO.W sign-extends the old word and uses only rs2[31:0].
Pitfalls / Common Confusions
rd holds the old 64-bit memory value before the operation, not the new XOR memory result.
AMOXOR.D is an RV64-only doubleword AMO and normally requires an 8-byte naturally aligned address; a misaligned atomicity granule PMA avoids an address-alignment exception only when all accessed bytes lie within one granule.
Memory receives the 64-bit result of oldDoubleword ^ rs2Doubleword; do not apply the 32-bit AMO.W sign-extension rule.
aq/rl constrain memory ordering only; they do not change this AMO.D instruction's data result.
FAQ
Do aq/rl bits change the XOR result of AMOXOR.D?
No. aq/rl only affect memory-ordering constraints; they do not change this AMO.D instruction's 64-bit data result.