AMOAND.D

RISC-V AMOAND.D Instruction Details

Instruction ManualR-type

RV64 atomic 64-bit doubleword bitwise AND: rd returns the old memory value, while memory receives oldDoubleword & rs2Doubleword

Instruction Syntax

amoand.d rd, rs2, (rs1)

Operand Breakdown

rd: receives the old memory value read atomically; for AMOCAS, its pre-execution value also supplies the compare value.

rs1: directly supplies the atomic-memory address; AMO assembly syntax has no offset immediate field.

rs2: supplies the AMO source data; for AMOCAS, it is the swap value stored when the comparison matches.

AMO-type is this site's presentation label for the AMO-specific R-type field layout: funct5, aq, rl, rs2, rs1, funct3, rd, and the AMO opcode encode the operation.

AZaamoAtomic Operation

Related Search Terms

AMOAND.D instruction RISC-V AMOAND.D amoand.d syntax amoand.d encoding atomic bitwise AND doubleword AMOAND.D old value AMO.D bitwise AND

Instruction Behavior

AMOAND.D performs an atomic read-modify-write on the 64-bit doubleword addressed by rs1: it first reads the old memory doubleword into rd, then computes oldDoubleword & rs2Doubleword using bitwise AND semantics and writes the 64-bit result back to the same address. The operation uses matching bit positions from the old doubleword and the rs2 doubleword. aq/rl bits affect memory ordering only; they do not change the data result.

AMOAND.D Atomic Decode And Execute Animation

Shows A / Zaamo doubleword atomic field decode, aq/rl ordering bits, a memory read, and RMW state update.

rs2

rs1

amoand.d

)

Execution ContextXLENmemory addressold memory doublewordrs2 (64-bit register)aqrlPMA is present and all accessed bytes are in one misaligned atomicity granule

31..27

24..20

19..15

14..12

11..7

6..0

01100

funct5

01011

rs2

01010

rs1

011

funct3

00101

0101111

opcode

Atomic Data Path

instruction

0x60B532AF

opcode

0101111 -> AMO

funct3

011 -> doubleword width

funct5

01100 -> AMOAND.D

aq / rl

0/0 -> unordered

rd / rs2 / rs1

t0(x5) / a1(x11)=0x0FF00000000000F0 / a0(x10)=0x0000000000001000

memory read

mem[0x0000000000001000] -> old doubleword 0xF0F000000000000F

RMW

0xF0F000000000000F & 0x0FF00000000000F0 -> 0x00F0000000000000

rd / memory

t0(x5) = 0xF0F000000000000F; mem[0x0000000000001000] = 0x00F0000000000000

Current Step

Concept Step: receive the 32-bit atomic instruction encoding

A / Zaamo-extension doubleword atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.

encoding: 0x60B532AF

syntax : amoand.d t0(x5), a1(x11), (a0(x10))

result : t0(x5) = 0xF0F000000000000F; mem[0x0000000000001000] = 0x00F0000000000000

64-bit Doubleword Result View

This animation shows ISA-visible atomic read-modify-write, compare-and-swap, LR/SC reservation state, and ordering bits, not any specific CPU cache-coherence implementation, pipeline, or timing.

Quick Understanding & Search Notes

AMOAND.D is an RV64 64-bit AMO.D read-modify-write instruction. On a successful access with rd other than x0, rd returns the old doubleword before the operation; only the result of oldDoubleword & rs2Doubleword is written back to memory, so keep old-value return separate from memory update.

funct5=01100, funct3=011, and opcode=0101111 identify AMOAND.D; aq/rl bits do not change the data calculation.

rd receives the old 64-bit memory doubleword before the operation; memory receives the 64-bit result computed by this AMO.D instruction.

AMOAND.D is an RV64-only doubleword AMO and normally requires 8-byte natural alignment; alignment is relaxed only when a misaligned atomicity granule PMA is present and all accessed bytes are within one granule.

AMOAND.D is a 64-bit bitwise logical AMO; each result bit comes from the same bit position of the old doubleword and the rs2 doubleword.

These read-modify-write effects assume a successful access. With rd=x0, the old-value register write is discarded but memory is still updated. rs2 uses its pre-execution value even when it overlaps rd. The target memory region must support this AMO width and operation.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — A Extension, Version 2.1 The RISC-V Instruction Set Manual, Volume II: Privileged Architecture — Misaligned Atomicity Granule PMA

Common Usage Scenarios

Bit Operations & Masks

Successful 64-bit access example: a2=0x1000, old memory=5, a1=3; amoand.d a0, a1, (a2) returns a0=5 and updates memory to 1. The address is naturally aligned and the region supports this AMO.

Atomic & Sync

Successful 64-bit access example: a2=0x1000, old memory=5, a1=3; amoand.d a0, a1, (a2) returns a0=5 and updates memory to 1. The address is naturally aligned and the region supports this AMO.

RV64 Operations

Successful 64-bit access example: a2=0x1000, old memory=5, a1=3; amoand.d a0, a1, (a2) returns a0=5 and updates memory to 1. The address is naturally aligned and the region supports this AMO.

Pre-Use Checklist

Syntax Check

rd, rs2, and rs1 select x0–x31 or their ABI names; syntax is rd, rs2, (rs1), with no rs3 or offset immediate.
Check funct5 for the operation and funct3 for access width; aq/rl are separate ordering bits, not a fixed funct7 constant.

Semantic Check

Check natural alignment or the misaligned atomicity granule PMA condition; the target region must support this AMO width and operation.
On success, rd receives old memory and the computed result goes to memory; rd=x0 discards only register writeback. On RV64, AMO.W sign-extends the old word and uses only rs2[31:0].

Pitfalls / Common Confusions

rd holds the old 64-bit memory value before the operation, not the new bitwise AND memory result.

Memory receives the 64-bit result of oldDoubleword & rs2Doubleword; do not apply the 32-bit AMO.W sign-extension rule.

aq/rl constrain memory ordering only; they do not change this AMO.D instruction's data result.

FAQ

Does AMOAND.D place the new memory result in rd?

No. AMOAND.D places the old 64-bit memory value before the operation in rd; the result of oldDoubleword & rs2Doubleword is written back to memory.

Do aq/rl bits change the bitwise AND result of AMOAND.D?

No. aq/rl only affect memory-ordering constraints; they do not change this AMO.D instruction's 64-bit data result.

RISC-V AMOAND.D Instruction Details

Instruction Syntax

Instruction Behavior

AMOAND.D Atomic Decode And Execute Animation

Concept Step: receive the 32-bit atomic instruction encoding

Quick Understanding & Search Notes

Common Usage Scenarios

Pre-Use Checklist

Pitfalls / Common Confusions

FAQ

Does AMOAND.D place the new memory result in rd?

Do aq/rl bits change the bitwise AND result of AMOAND.D?

Related Instructions & Pseudo-instructions