AMOAND.W

RISC-V AMOAND.W Instruction Details

Instruction ManualR-type

Atomic 32-bit word bitwise AND: rd returns the old memory word, while memory receives the 32-bit result of oldWord & rs2LowWord

Instruction Syntax

amoand.w rd, rs2, (rs1)

Operand Breakdown

rd: receives the old memory value read atomically; for AMOCAS, its pre-execution value also supplies the compare value.

rs1: directly supplies the atomic-memory address; AMO assembly syntax has no offset immediate field.

rs2: supplies the AMO source data; for AMOCAS, it is the swap value stored when the comparison matches.

AMO-type is this site's presentation label for the AMO-specific R-type field layout: funct5, aq, rl, rs2, rs1, funct3, rd, and the AMO opcode encode the operation.

AZaamoAtomic

Related Search Terms

AMOAND.W instruction RISC-V AMOAND.W amoand.w syntax amoand.w encoding atomic bitwise AND word AMOAND.W old value RISC-V AMO bitwise AND

Instruction Behavior

AMOAND.W performs an atomic read-modify-write on the 32-bit word addressed by rs1: it first reads the old memory word and sign-extends it into rd, then bitwise-ANDs the old word with the low 32 bits of rs2. The resulting 32-bit word is written back to the same address. aq/rl bits affect memory ordering only; they do not change the bitwise AND data result.

AMOAND.W Atomic Decode And Execute Animation

Shows A / Zaamo word atomic field decode, aq/rl ordering bits, a memory read, and RMW state update.

rs2

rs1

amoand.w

)

Execution ContextXLENmemory addressold memory wordrs2 (32-bit register)aqrlPMA is present and all accessed bytes are in one misaligned atomicity granule

31..27

24..20

19..15

14..12

11..7

6..0

01100

funct5

01011

rs2

01010

rs1

010

funct3

00101

0101111

opcode

Atomic Data Path

instruction

0x60B522AF

opcode

0101111 -> AMO

funct3

010 -> word width

funct5

01100 -> AMOAND.W

aq / rl

0/0 -> unordered

rd / rs2 / rs1

t0(x5) / a1(x11)[31:0]=0x0FF00FF0 / a0(x10)=0x00001000

memory read

mem[0x00001000] -> old word 0xF0F0000F

RMW

0xF0F0000F & 0x0FF00FF0 -> 0x00F00000

rd / memory

t0(x5) = 0xF0F0000F; mem[0x00001000] = 0x00F00000

Current Step

Concept Step: receive the 32-bit atomic instruction encoding

A / Zaamo-extension word atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.

encoding: 0x60B522AF

syntax : amoand.w t0(x5), a1(x11), (a0(x10))

result : t0(x5) = 0xF0F0000F; mem[0x00001000] = 0x00F00000

32-bit Word Result View

This animation shows ISA-visible atomic read-modify-write, compare-and-swap, LR/SC reservation state, and ordering bits, not any specific CPU cache-coherence implementation, pipeline, or timing.

Quick Understanding & Search Notes

AMOAND.W is used for atomic bit clearing or masked updates. On a successful access with rd other than x0, rd receives the sign-extended old memory word; the new 32-bit word after the bitwise AND operation is written only to memory.

funct5=01100, funct3=010, and opcode=0101111 identify AMOAND.W; aq/rl bits do not change the data calculation.

rd receives the old memory word before the operation; memory receives the 32-bit result of oldWord & rs2LowWord.

AMO.W is a word-width AMO; on RV64, the old word in rd is sign-extended to XLEN.

AMOAND.W is a bitwise word operation; each result bit comes from the same bit position of the old word and rs2 low word.

Normally requires 4-byte natural alignment; alignment is relaxed only when a misaligned atomicity granule PMA is present and all accessed bytes are within one granule.

These read-modify-write effects assume a successful access. With rd=x0, the old-value register write is discarded but memory is still updated. rs2 uses its pre-execution value even when it overlaps rd. The target memory region must support this AMO width and operation.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — A Extension, Version 2.1 The RISC-V Instruction Set Manual, Volume II: Privileged Architecture — Misaligned Atomicity Granule PMA

Common Usage Scenarios

Atomic & Sync

Successful 32-bit access example: a2=0x1000, old memory=5, a1=3; amoand.w a0, a1, (a2) returns a0=5 and updates memory to 1. The address is naturally aligned and the region supports this AMO.

Bit Operations & Masks

Successful 32-bit access example: a2=0x1000, old memory=5, a1=3; amoand.w a0, a1, (a2) returns a0=5 and updates memory to 1. The address is naturally aligned and the region supports this AMO.

Pre-Use Checklist

Syntax Check

rd, rs2, and rs1 select x0–x31 or their ABI names; syntax is rd, rs2, (rs1), with no rs3 or offset immediate.
Check funct5 for the operation and funct3 for access width; aq/rl are separate ordering bits, not a fixed funct7 constant.

Semantic Check

Check natural alignment or the misaligned atomicity granule PMA condition; the target region must support this AMO width and operation.
On success, rd receives old memory and the computed result goes to memory; rd=x0 discards only register writeback. On RV64, AMO.W sign-extends the old word and uses only rs2[31:0].

Pitfalls / Common Confusions

rd holds the old memory word before the operation, not the new bitwise AND memory result.

AMO.W atomically accesses a 32-bit word; on RV64, the old word loaded into rd is sign-extended to XLEN.

Only the low 32-bit word of rs2 participates in the calculation, and memory receives a 32-bit word result.

aq/rl constrain memory ordering only; they do not change the value of oldWord & rs2LowWord.

Normally requires a 4-byte naturally aligned address; alignment is relaxed only when a misaligned atomicity granule PMA is present and all accessed bytes are within one granule.

FAQ

Does AMOAND.W place the new memory result in rd?

No. AMOAND.W places the old memory word before the operation in rd; the result of oldWord & rs2LowWord is written back to memory.

Do aq/rl bits change the bitwise AND result of AMOAND.W?

No. aq/rl only affect memory-ordering constraints; they do not change this AMO.W instruction's 32-bit data result.