Does AMOSWAP.D write the new value or old value to rd?
rd receives the old value. AMOSWAP.D first reads the old 64-bit memory value into rd, then writes the 64-bit rs2 value to memory.
AMOSWAP.D
RISC-V AMOSWAP.D Instruction Details
Instruction ManualR-typeRV64 atomic 64-bit doubleword swap: rd returns the old memory value, while memory receives the 64-bit value from rs2
Instruction Syntax
amoswap.d rd, rs2, (rs1)
Operand Breakdown
rd: receives the old memory value read atomically; for AMOCAS, its pre-execution value also supplies the compare value.
rs1: directly supplies the atomic-memory address; AMO assembly syntax has no offset immediate field.
rs2: supplies the AMO source data; for AMOCAS, it is the swap value stored when the comparison matches.
AMO-type is this site's presentation label for the AMO-specific R-type field layout: funct5, aq, rl, rs2, rs1, funct3, rd, and the AMO opcode encode the operation.
AZaamoAtomic
Instruction Behavior
The following semantics assume the target region supports this AMO width and operation and the access succeeds. AMOSWAP.D performs an atomic read-modify-write on the 64-bit doubleword addressed by rs1: it reads the old memory doubleword into rd and then writes the 64-bit value from rs2 back to the same address. It is an RV64 A/Zaamo instruction and does not use an LR/SC reservation; aq/rl add ordering only in the accessed memory or I/O address domain, and ordering across both domains still needs FENCE. rs2 uses its pre-execution value; rd=x0 discards only the old-value register writeback, while the memory operation still occurs.
AMOSWAP.D Atomic Decode And Execute Animation
Shows A / Zaamo doubleword atomic field decode, aq/rl ordering bits, a memory read, and RMW state update.
rd
rs2
rs1
amoswap.d,,()
Execution Context
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00001
funct5
1
aq
0
rl
01011
rs2
01010
rs1
011
funct3
00101
rd
0101111
opcode
Atomic Data Path
instruction
0x0CB532AF
opcode
0101111 -> AMO
funct3
011 -> doubleword width
funct5
00001 -> AMOSWAP.D
aq / rl
1/0 -> acquire
rd / rs2 / rs1
t0(x5) / a1(x11)=0x000000000000007F / a0(x10)=0x0000000000001000
memory read
mem[0x0000000000001000] -> old doubleword 0x8000000000000002
RMW
new memory doubleword = rs2 doubleword 0x000000000000007F
rd / memory
t0(x5) = 0x8000000000000002; mem[0x0000000000001000] = 0x000000000000007F
Current Step
Concept Step: receive the 32-bit atomic instruction encoding
A / Zaamo-extension doubleword atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.
encoding: 0x0CB532AF
syntax : amoswap.d.aq t0(x5), a1(x11), (a0(x10))
result : t0(x5) = 0x8000000000000002; mem[0x0000000000001000] = 0x000000000000007F
64-bit Doubleword Result View
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Assumes the region supports this AMO and the access succeeds. Shows the operation, old-value return, memory update and aq/rl ordering in the accessed domain. Steps are a teaching sequence; access faults, CPU cache coherence, pipelines and timing are not modeled.
Quick Understanding & Search Notes
AMOSWAP.D is a 64-bit atomic swap: on successful access with rd≠x0, rd gets the old memory doubleword before the swap, and memory gets the 64-bit rs2 value. It is not an LR/SC sequence and does not write the new value to rd.
funct5=00001, funct3=011, and opcode=0101111 identify AMOSWAP.D.
rd receives the old 64-bit memory value before the swap; memory receives the 64-bit value from rs2.
AMOSWAP.D is an RV64-only doubleword AMO and normally requires an 8-byte naturally aligned address. A misaligned atomicity granule PMA avoids an address-alignment exception when all accessed bytes lie in one granule.
aq/rl bits provide ordering constraints and do not change old-value return or memory writeback data.
Common Usage Scenarios
Atomic & Sync
Successful 64-bit access example: a2=0x1000, old memory=5, a1=3; amoswap.d a0, a1, (a2) returns a0=5 and updates memory to 3. The address is naturally aligned and the region supports this AMO.
RV64 Operations
Successful 64-bit access example: a2=0x1000, old memory=5, a1=3; amoswap.d a0, a1, (a2) returns a0=5 and updates memory to 3. The address is naturally aligned and the region supports this AMO.
Pre-Use Checklist
Syntax Check
- rd, rs2, and rs1 select x0–x31 or their ABI names; syntax is rd, rs2, (rs1), with no rs3 or offset immediate.
- Check funct5 for the operation and funct3 for access width; aq/rl are separate ordering bits, not a fixed funct7 constant.
Semantic Check
- Check natural alignment or the misaligned atomicity granule PMA condition; the target region must support this AMO width and operation.
- On success, rd receives old memory and the computed result goes to memory; rd=x0 discards only register writeback. On RV64, AMO.W sign-extends the old word and uses only rs2[31:0].
Pitfalls / Common Confusions
rd returns the old 64-bit memory value before the swap
Memory receives the 64-bit value from rs2, not rd
An 8-byte naturally aligned address is normally required; a misaligned atomicity granule PMA avoids an address-alignment exception when all accessed bytes lie in one granule
RV64 only
aq/rl do not change the swapped data result
FAQ
Does AMOSWAP.D require an LR.D reservation?
No. AMOSWAP.D is a single AMO read-modify-write instruction and does not depend on LR/SC reservation state.