AMOSWAP.D
RISC-V AMOSWAP.D Instruction Details
Instruction ManualR-typeAtomically swap 64-bit doubleword: rd = *rs1, *rs1 = rs2 (RV64 only)
Instruction Syntax
amoswap.d rd, rs2, (rs1)
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
AZaamoAtomic Operation
Instruction Behavior
AMOSWAP.D atomically loads the 64-bit doubleword from the address in rs1 into rd, then stores rs2 to the same address. This is an RV64A instruction. Supports aq/rl bits for memory ordering.
Common Usage Scenarios
Address & Pointer
Understand this scenario with real code like «amoswap.d.aq t0, t1, (a0) # atomic swap 64-bit *a0 with t1».
Atomic & Sync
Understand this scenario with real code like «amoswap.d.aq t0, t1, (a0) # atomic swap 64-bit *a0 with t1».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Address must be 8-byte aligned
RV64 only