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AMOSWAP.D

RISC-V AMOSWAP.D Instruction Details

Instruction ManualR-type

RV64 atomic 64-bit doubleword swap: rd returns the old memory value, while memory receives the 64-bit value from rs2

Instruction Syntax

amoswap.d rd, rs2, (rs1)
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
AZaamoAtomic
Related Search Terms
AMOSWAP.D instructionRISC-V AMOSWAP.Damoswap.d syntaxamoswap.d encodingatomic swap doublewordAMOSWAP.D old valueRISC-V AMO swap

Instruction Behavior

AMOSWAP.D performs an atomic read-modify-write on the 64-bit doubleword addressed by rs1: it reads the old memory doubleword into rd and then writes the 64-bit value from rs2 back to the same address. It is an RV64 A/Zaamo instruction and does not use an LR/SC reservation; aq/rl bits affect memory ordering only.

AMOSWAP.D Atomic Decode And Execute Animation

Shows A-extension doubleword atomic field decode, aq/rl ordering bits, memory read, and RMW state update.

rd
rs2
rs1
amoswap.d
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Execution Context
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00001
funct5
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aq
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rl
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funct3
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0101111
opcode
Atomic Data Path
instruction
0x0CB532AF
opcode
0101111 -> AMO
funct3
011 -> doubleword width
funct5
00001 -> AMOSWAP.D
aq / rl
1/0 -> acquire
rd / rs2 / rs1
t0(x5) / a1(x11)=0x000000000000007F / a0(x10)=0x00001000
memory read
mem[0x00001000] -> old doubleword 0x8000000000000002
RMW
new memory doubleword = rs2 doubleword 0x000000000000007F
rd / memory
t0(x5) = 0x00000002; mem[0x00001000] = 0x000000000000007F
Current Step

Concept Step: receive the 32-bit atomic instruction encoding

A-extension doubleword atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.

encoding: 0x0CB532AF
syntax : amoswap.d t0(x5), a1(x11), (a0(x10))
result : t0(x5) = 0x00000002; mem[0x00001000] = 0x000000000000007F
64-bit Doubleword Result View
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This animation shows ISA-visible atomic read-modify-write, compare-and-swap, LR/SC reservation state, and ordering bits, not any specific CPU cache-coherence implementation, pipeline, or timing.

Quick Understanding & Search Notes

AMOSWAP.D is a 64-bit atomic swap: rd gets the old memory doubleword before the swap, and memory gets the 64-bit rs2 value. It is not an LR/SC sequence and does not write the new value to rd.

funct5=00001, funct3=011, and opcode=0101111 identify AMOSWAP.D.
rd receives the old 64-bit memory value before the swap; memory receives the 64-bit value from rs2.
AMOSWAP.D is an RV64-only doubleword AMO, and the address must be naturally aligned to 8 bytes.
aq/rl bits provide ordering constraints and do not change old-value return or memory writeback data.
RISC-V Unprivileged ISA Manual: A Extension for Atomic Instructions

Common Usage Scenarios

Atomic & Sync

Understand this scenario with real code like «amoswap.d.aq t0, t1, (a0) # t0 = old 64-bit *a0; *a0 = t1».

RV64 Operations

Understand this scenario with real code like «amoswap.d.aq t0, t1, (a0) # t0 = old 64-bit *a0; *a0 = t1».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

rd returns the old 64-bit memory value before the swap
Memory receives the 64-bit value from rs2, not rd
Address must be naturally aligned to 8 bytes
RV64 only
aq/rl do not change the swapped data result

FAQ

Does AMOSWAP.D write the new value or old value to rd?

rd receives the old value. AMOSWAP.D first reads the old 64-bit memory value into rd, then writes the 64-bit rs2 value to memory.

Does AMOSWAP.D require an LR.D reservation?

No. AMOSWAP.D is a single AMO read-modify-write instruction and does not depend on LR/SC reservation state.