AMOADD.D
RISC-V AMOADD.D Instruction Details
Instruction ManualR-typeAtomically add 64-bit doubleword: rd = *rs1, *rs1 += rs2 (RV64 only)
Instruction Syntax
amoadd.d rd, rs2, (rs1)
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
AZaamoAtomic Operation
Instruction Behavior
AMOADD.D atomically loads the 64-bit doubleword from the address in rs1 into rd, adds rs2, and stores back. This is an RV64A instruction. Supports aq/rl bits. Commonly used for 64-bit atomic counters.
Common Usage Scenarios
Debug & Monitoring
Understand this scenario with real code like «amoadd.d a0, a1, (a2) # a0 = *a2; *a2 += a1 (64-bit)».
Loops & Iteration
Understand this scenario with real code like «amoadd.d a0, a1, (a2) # a0 = *a2; *a2 += a1 (64-bit)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Overflow wraps (mod 2^64)
Returns old value before add