Does AMOADD.D place the added result in rd?
No. AMOADD.D places the old 64-bit memory value before the add in rd; the low 64-bit added result is written back to memory.
AMOADD.D
RISC-V AMOADD.D Instruction Details
Instruction ManualR-typeRV64 atomic 64-bit doubleword add: rd returns the old memory value, while memory receives the low 64-bit result of old value plus rs2
Instruction Syntax
amoadd.d rd, rs2, (rs1)
Operand Breakdown
rd: receives the old memory value read atomically; for AMOCAS, its pre-execution value also supplies the compare value.
rs1: directly supplies the atomic-memory address; AMO assembly syntax has no offset immediate field.
rs2: supplies the AMO source data; for AMOCAS, it is the swap value stored when the comparison matches.
AMO-type is this site's presentation label for the AMO-specific R-type field layout: funct5, aq, rl, rs2, rs1, funct3, rd, and the AMO opcode encode the operation.
AZaamoAtomic
Instruction Behavior
AMOADD.D performs an atomic read-modify-write on the 64-bit doubleword addressed by rs1: it reads the old memory value into rd, adds that old value to the 64-bit value from rs2, and writes the low 64-bit result back to the same address. The addition wraps as a 64-bit doubleword; aq/rl bits affect memory ordering and do not change the arithmetic result.
AMOADD.D Atomic Decode And Execute Animation
Shows A / Zaamo doubleword atomic field decode, aq/rl ordering bits, a memory read, and RMW state update.
rd
rs2
rs1
amoadd.d,,()
Execution Context
31..27
26
25
24..20
19..15
14..12
11..7
6..0
00000
funct5
0
aq
0
rl
01011
rs2
01010
rs1
011
funct3
00101
rd
0101111
opcode
Atomic Data Path
instruction
0x00B532AF
opcode
0101111 -> AMO
funct3
011 -> doubleword width
funct5
00000 -> AMOADD.D
aq / rl
0/0 -> unordered
rd / rs2 / rs1
t0(x5) / a1(x11)=0x0000000000000020 / a0(x10)=0x0000000000001000
memory read
mem[0x0000000000001000] -> old doubleword 0xFFFFFFFFFFFFFFF0
RMW
0xFFFFFFFFFFFFFFF0 + 0x0000000000000020 -> 0x0000000000000010
rd / memory
t0(x5) = 0xFFFFFFFFFFFFFFF0; mem[0x0000000000001000] = 0x0000000000000010
Current Step
Concept Step: receive the 32-bit atomic instruction encoding
A / Zaamo-extension doubleword atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.
encoding: 0x00B532AF
syntax : amoadd.d t0(x5), a1(x11), (a0(x10))
result : t0(x5) = 0xFFFFFFFFFFFFFFF0; mem[0x0000000000001000] = 0x0000000000000010
64-bit Doubleword Addition
old doubleword
0xFFFFFFFFFFFFFFF0
rs2 doubleword
0x0000000000000020
low 64-bit sum
0xFFFFFFFFFFFFFFF0 + 0x0000000000000020
memory result
0x0000000000000010
AMOADD.D uses full 64-bit doubleword addition and writes the low 64-bit result to memory; this view avoids per-bit equations that would hide the carry chain.
This animation shows ISA-visible atomic read-modify-write, compare-and-swap, LR/SC reservation state, and ordering bits, not any specific CPU cache-coherence implementation, pipeline, or timing.
Quick Understanding & Search Notes
AMOADD.D is commonly used for RV64 64-bit atomic counter updates. rd returns the old doubleword before the add, while memory receives the low 64-bit result of old value plus rs2; do not mistake rd for the new sum.
funct5=00000, funct3=011, and opcode=0101111 identify AMOADD.D; aq/rl bits do not change the arithmetic calculation.
rd receives the old 64-bit memory value before the add; memory receives the low 64-bit result of old value plus rs2.
AMOADD.D is an RV64-only doubleword AMO and normally requires 8-byte natural alignment; alignment is relaxed only when a misaligned atomicity granule PMA is present and all accessed bytes are within one granule.
The 64-bit addition wraps at doubleword width, and the page animation shows the low 64 bits written back to memory.
These read-modify-write effects assume a successful access. With rd=x0, the old-value register write is discarded but memory is still updated. rs2 uses its pre-execution value even when it overlaps rd. The target memory region must support this AMO width and operation.
Common Usage Scenarios
Atomic & Sync
Successful 64-bit access example: a2=0x1000, old memory=5, a1=3; amoadd.d a0, a1, (a2) returns a0=5 and updates memory to 8. The address is naturally aligned and the region supports this AMO.
RV64 Operations
Successful 64-bit access example: a2=0x1000, old memory=5, a1=3; amoadd.d a0, a1, (a2) returns a0=5 and updates memory to 8. The address is naturally aligned and the region supports this AMO.
Pre-Use Checklist
Syntax Check
- rd, rs2, and rs1 select x0–x31 or their ABI names; syntax is rd, rs2, (rs1), with no rs3 or offset immediate.
- Check funct5 for the operation and funct3 for access width; aq/rl are separate ordering bits, not a fixed funct7 constant.
Semantic Check
- Check natural alignment or the misaligned atomicity granule PMA condition; the target region must support this AMO width and operation.
- On success, rd receives old memory and the computed result goes to memory; rd=x0 discards only register writeback. On RV64, AMO.W sign-extends the old word and uses only rs2[31:0].
Pitfalls / Common Confusions
The 64-bit addition wraps modulo 2^64
rd returns the old memory value before the add, not the new sum
Normally requires an 8-byte naturally aligned address; alignment is relaxed only when a misaligned atomicity granule PMA is present and all accessed bytes are within one granule
RV64 only
aq/rl do not change the addition result
FAQ
Does AMOADD.D trap on addition overflow?
No. The doubleword addition wraps at 64 bits, and the low 64-bit result is written back.