LR.D
RISC-V LR.D Instruction Details
Instruction ManualR-typeLoad 64-bit doubleword from address in rs1 and register a reservation for SC.D (RV64 only)
Instruction Syntax
lr.d rd, (rs1)
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
AZalrscAtomic Operation
Instruction Behavior
LR.D loads a 64-bit doubleword from the address in rs1 into rd and registers a reservation set. This is an RV64A instruction, similar to LR.W but operating on 64-bit values. The reservation is used by SC.D for conditional store. Supports aq/rl bits for memory ordering.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «lr.d.aq t0, (a0) # load doubleword from *a0 with acquire ordering».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Address must be 8-byte aligned
RV64 only
New LR.D overwrites previous reservation