Does LR.D write memory?
No. LR.D reads the old 64-bit value into rd and creates a reservation set; a later SC.D attempts the memory write.
LR.D
RISC-V LR.D Instruction Details
Instruction ManualR-typeOn RV64, atomically read a 64-bit doubleword into rd and create a reservation set for a later SC.D
Instruction Syntax
lr.d rd, (rs1)
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
AZalrscAtomic
Instruction Behavior
LR.D atomically reads a 64-bit doubleword from the naturally aligned address in rs1, writes the old value to rd, and creates a reservation set covering the accessed bytes. It is an RV64 A/Zalrsc instruction and does not write memory; a later SC.D uses the reservation to decide whether the conditional store succeeds. aq/rl bits affect memory ordering only and do not change the loaded value.
LR.D Atomic Decode And Execute Animation
Shows A-extension doubleword atomic field decode, aq/rl ordering bits, memory read, and RMW state update.
rd
rs1
lr.d,()
Execution Context
31..27
26
25
24..20
19..15
14..12
11..7
6..0
00010
funct5
1
aq
0
rl
00000
rs2=00000
01010
rs1
011
funct3
00101
rd
0101111
opcode
Atomic Data Path
instruction
0x140532AF
opcode
0101111 -> AMO
funct3
011 -> doubleword width
funct5
00010 -> LR.D
aq / rl
1/0 -> acquire
rd / rs1
t0(x5) / a0(x10)=0x00001000
memory read
mem[0x00001000] -> old doubleword 0x0000000000000005
reservation
create reservation for 8 bytes at 0x00001000
rd / reservation
t0(x5) = 0x00000005; reservation set created
Current Step
Concept Step: receive the 32-bit atomic instruction encoding
A-extension doubleword atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.
encoding: 0x140532AF
syntax : lr.d t0(x5), (a0(x10))
result : t0(x5) = 0x00000005; reservation set created
This animation shows ISA-visible atomic read-modify-write, compare-and-swap, LR/SC reservation state, and ordering bits, not any specific CPU cache-coherence implementation, pipeline, or timing.
Quick Understanding & Search Notes
LR.D is the 64-bit first step of an RV64 LR/SC sequence: it reads the old doubleword into rd and creates a reservation set. It does not write memory and is not just an ordinary ld, because a later SC.D consumes the reservation.
funct5=00010, funct3=011, and opcode=0101111 identify LR.D; the encoded rs2 field must be x0.
LR.D is an RV64-only doubleword operation with 64-bit memory width; it does not use the AMO.W 32-bit sign-extension rule.
The target address must be naturally aligned for a doubleword; misaligned access raises an address-misaligned or access-fault exception.
aq/rl bits only affect memory-ordering constraints and do not change the semantics of reading the old value and creating the reservation.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «lr.d.aq t0, (a0) # load 64-bit doubleword from *a0 and create a reservation».
RV64 Operations
Understand this scenario with real code like «lr.d.aq t0, (a0) # load 64-bit doubleword from *a0 and create a reservation».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Address must be naturally aligned to 8 bytes
RV64 only
A new LR.D replaces the same hart previous reservation
LR.D creates a reservation but does not guarantee that a later SC.D succeeds
FAQ
What is the key difference between LR.D and LR.W?
LR.D is RV64-only, accesses a 64-bit doubleword, and requires 8-byte alignment; LR.W accesses a 32-bit word.