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SC.D

RISC-V SC.D Instruction Details

Instruction ManualR-type

On RV64, conditionally store a 64-bit doubleword according to reservation state; success writes rd=0, failure writes nonzero and leaves memory unchanged

Instruction Syntax

sc.d rd, rs2, (rs1)
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
AZalrscAtomic
Related Search Terms
SC.D instructionRISC-V SC.Dsc.d syntaxsc.d encodingStore-Conditional Doublewordsc.d success failure64-bit LR SC

Instruction Behavior

SC.D uses the 64-bit doubleword in rs2 as the candidate store value. It writes that value to memory and sets rd=0 only if the current hart has a valid reservation containing the target bytes addressed by rs1; on failure it does not write memory and writes a nonzero failure code to rd. Whether it succeeds or fails, SC.D invalidates the current reservation.

SC.D Atomic Decode And Execute Animation

Shows A-extension doubleword atomic field decode, aq/rl ordering bits, memory read, and RMW state update.

rd
rs2
rs1
sc.d
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Execution Context
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00011
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rl
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Atomic Data Path
instruction
0x1AB5332F
opcode
0101111 -> AMO
funct3
011 -> doubleword width
funct5
00011 -> SC.D
aq / rl
0/1 -> release
rd / rs2 / rs1
t1(x6) / a1(x11)=0x0000000000000009 / a0(x10)=0x00001000
memory read
mem[0x00001000] -> old doubleword 0x0000000000000005
condition
SC succeeds -> store 0x0000000000000009
rd / memory / reservation
t1(x6) = 0x00000000; mem[0x00001000] = 0x0000000000000009; reservation invalidated
Current Step

Concept Step: receive the 32-bit atomic instruction encoding

A-extension doubleword atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.

encoding: 0x1AB5332F
syntax : sc.d t1(x6), a1(x11), (a0(x10))
result : t1(x6) = 0x00000000; mem[0x00001000] = 0x0000000000000009; reservation invalidated
64-bit Doubleword Result View
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This animation shows ISA-visible atomic read-modify-write, compare-and-swap, LR/SC reservation state, and ordering bits, not any specific CPU cache-coherence implementation, pipeline, or timing.

Quick Understanding & Search Notes

SC.D is the conditional write point of an RV64 LR/SC sequence. On success it stores the 64-bit rs2 value and writes rd=0; on failure memory keeps the old value and rd is nonzero.

funct5=00011, funct3=011, and opcode=0101111 identify SC.D; rd is the status-result register.
rs2 supplies the 64-bit candidate store data; rd receives the 0 or nonzero success/failure status.
On SC.D failure, memory is not written; both success and failure invalidate the current hart reservation.
The architectural contract only guarantees a nonzero failure code; portable software should not depend on a specific failure value.
RISC-V Unprivileged ISA Manual: A Extension for Atomic Instructions

Common Usage Scenarios

Atomic & Sync

Understand this scenario with real code like «sc.d.rl t0, a1, (a0) # store 64-bit a1 to *a0 if the reservation is valid; t0=0 on success».

RV64 Operations

Understand this scenario with real code like «sc.d.rl t0, a1, (a0) # store 64-bit a1 to *a0 if the reservation is valid; t0=0 on success».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

SC.D may fail, so software must check rd
The failure code is only guaranteed to be nonzero; do not depend on a specific value
Address must be naturally aligned to 8 bytes
RV64 only
SC.D invalidates the reservation on both success and failure

FAQ

Does rd hold the stored data when SC.D succeeds?

No. rd is the status-result register: success writes 0 and failure writes nonzero; the memory data comes from rs2.

Does SC.D modify memory on failure?

No. On failure, SC.D does not perform the memory write; it only writes a nonzero failure code to rd and invalidates the reservation.