SC.D
RISC-V SC.D Instruction Details
Instruction ManualR-typeConditionally store 64-bit doubleword: writes rs2 if reservation holds, rd gets success/failure (RV64 only)
Instruction Syntax
sc.d rd, rs2, (rs1)
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
AZalrscAtomic Operation
Instruction Behavior
SC.D conditionally writes the 64-bit doubleword in rs2 to the address in rs1. Succeeds only if reservation is valid and set contains target bytes. Writes 0 to rd on success, nonzero on failure. Invalidates reservation regardless. RV64A only.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «sc.d.rl t0, a1, (a0) # try store a1 (64-bit) to *a0 with release ordering».
RV64-Specific Operations
Understand this scenario with real code like «sc.d.rl t0, a1, (a0) # try store a1 (64-bit) to *a0 with release ordering».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
May spuriously fail, requires retry loop
Address must be 8-byte aligned
RV64 only