Why does SC.W write 0 to rd on success?
SC.W uses rd as a status-result register. The official semantics define 0 for success and nonzero for failure, letting software decide whether to exit or retry the LR/SC loop.
SC.W
RISC-V SC.W Instruction Details
Instruction ManualR-typeAtomically conditionally store a 32-bit word if the reservation is valid; success writes memory and rd=0, failure leaves memory unchanged and rd nonzero
Instruction Syntax
sc.w rd, rs2, (rs1)
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
AZalrscAtomic
Instruction Behavior
SC.W takes the low 32 bits of rs2 as the candidate store value and writes it to the address in rs1 only if the reservation from the most recent LR.W is still valid and the reservation set contains the target bytes. On success, rd receives zero; on failure, memory is not written and rd receives a nonzero failure code. Whether it succeeds or fails, SC.W invalidates the current hart reservation.
SC.W Atomic Decode And Execute Animation
Shows A-extension word atomic field decode, aq/rl ordering bits, memory read, and RMW state update.
rd
rs2
rs1
sc.w,,()
Execution Context
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00011
funct5
0
aq
1
rl
01011
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01010
rs1
010
funct3
00110
rd
0101111
opcode
Atomic Data Path
instruction
0x1AB5232F
opcode
0101111 -> AMO
funct3
010 -> word width
funct5
00011 -> SC.W
aq / rl
0/1 -> release
rd / rs2 / rs1
t1(x6) / a1(x11)=0x00000009 / a0(x10)=0x00001000
memory read
mem[0x00001000] -> old word 0x00000005
condition
SC succeeds -> store 0x00000009
rd / memory / reservation
t1(x6) = 0x00000000; mem[0x00001000] = 0x00000009; reservation invalidated
Current Step
Concept Step: receive the 32-bit atomic instruction encoding
A-extension word atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.
encoding: 0x1AB5232F
syntax : sc.w t1(x6), a1(x11), (a0(x10))
result : t1(x6) = 0x00000000; mem[0x00001000] = 0x00000009; reservation invalidated
32-bit Word Result View
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This animation shows ISA-visible atomic read-modify-write, compare-and-swap, LR/SC reservation state, and ordering bits, not any specific CPU cache-coherence implementation, pipeline, or timing.
Quick Understanding & Search Notes
SC.W is the decision point in an LR/SC sequence: it is not an unconditional store. On success it writes memory and writes 0 to rd; on failure memory remains unchanged and rd receives a nonzero failure code.
funct5=00011, funct3=010, and opcode=0101111 identify SC.W; rd is the status-result register, not the data stored to memory.
rs2 supplies the candidate 32-bit memory data; rd receives the 0 or nonzero success/failure status.
On SC.W failure, memory is not written; both success and failure invalidate the current hart reservation.
The architectural contract only requires a nonzero failure code; portable software should not depend on a specific nonzero value.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «sc.w.rl t0, a1, (a0) # try store a1 to *a0 with release ordering, t0=0 on success».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
May spuriously fail, requires retry loop
Only check failure code for non-zero, don't depend on specific value
Code between LR/SC must follow constrained LR/SC loop rules
Address must be 4-byte aligned
FAQ
Does SC.W modify memory on failure?
No. On failure, SC.W does not perform the memory write; it only writes a nonzero failure code to rd and invalidates the current reservation.