Why does SC.W write 0 to rd on success?
SC.W uses rd as a status-result register. The official semantics define 0 for success and nonzero for failure, letting software decide whether to exit or retry the LR/SC loop.
SC.W
RISC-V SC.W Instruction Details
Instruction ManualR-typeRV32/RV64 32-bit store-conditional: success stores data and returns rd=0; failure performs no data store and returns nonzero.
Instruction Syntax
sc.w rd, rs2, (rs1)
Operand Breakdown
rd: receives zero on success or nonzero on failure; rd=x0 discards only status writeback.
rs1: supplies a naturally aligned 4-byte address directly, with no offset; rs2: supplies its pre-execution low 32 bits as store data.
Requires Zalrsc or A; SC.D is RV64-only. A valid reservation does not guarantee success, and both outcomes invalidate this hart's reservation.
AZalrscAtomic
Extension condition: RV32/RV64, requiring Zalrsc or the A extension that includes Zalrsc.
Instruction Behavior
SC.W uses rs1 as the address and rs2's low 32 bits as candidate data. Success stores data and writes zero to rd; failure performs no data store and writes a nonzero code to rd. Success requires a valid reservation from the most recent LR covering the written bytes, but a valid reservation does not guarantee success. Relevant writes by another hart, device writes to LR-accessed bytes, or an intervening SC force failure. Both outcomes invalidate this hart's reservation. SC must pass memory permission checks before retiring; side effects of implicit translation/protection accesses on failure are unspecified. On RV64, SC.W sign-extends its 32-bit status value to XLEN.
SC.W Atomic Decode And Execute Animation
Shows A / Zalrsc word atomic field decode, aq/rl ordering bits, reservation and permission checks, and store-conditional state update.
rd
rs2
rs1
sc.w,,()
Execution Context
This teaching toggle selects the SC success or failure outcome; success still depends on the most recent LR reservation and other architectural conditions, and a failure code is only guaranteed to be nonzero.
31..27
26
25
24..20
19..15
14..12
11..7
6..0
00011
funct5
0
aq
1
rl
01011
rs2
01010
rs1
010
funct3
00110
rd
0101111
opcode
Atomic Data Path
instruction
0x1AB5232F
opcode
0101111 -> AMO
funct3
010 -> word width
funct5
00011 -> SC.W
aq / rl
0/1 -> release
rd / rs2 / rs1
t1(x6) / a1(x11)=0x00000009 / a0(x10)=0x00001000
reservation / permissions
check the most recent LR reservation and store permissions for 0x00001000; no old-memory value is architecturally exposed
condition
Not computed
rd / memory / reservation
t1(x6) = unspecified initial value; SC not committed; this SC has not yet invalidated the reservation
Current Step
Concept Step: receive the 32-bit atomic instruction encoding
A / Zalrsc-extension word atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.
encoding: 0x1AB5232F
syntax : sc.w.rl t1(x6), a1(x11), (a0(x10))
Pending result : Not computed
Current architectural state
t1(x6) = unspecified initial value; SC not committed; this SC has not yet invalidated the reservation
Assumes successful fetch, a naturally aligned LR/SC-capable region and passed memory permission checks. The toggle chooses a permitted SC success/failure outcome; LR, the reservation set and other hart/device interference are not fully modeled. Failure performs no data store, but implicit translation/protection side effects are unspecified. aq/rl concerns only the accessed memory/I/O domain; steps are a teaching sequence.
Quick Understanding & Search Notes
SC.W is the decision point in an LR/SC sequence: it is not an unconditional store. On success it writes memory and writes 0 to rd; on failure it performs no data store and rd receives a nonzero failure code.
funct5=00011, funct3=010, and opcode=0101111 identify SC.W; rd is the status-result register, not the data stored to memory.
rs2 supplies the candidate 32-bit memory data; rd receives the 0 or nonzero success/failure status.
On SC.W failure, no data store is performed; both success and failure invalidate the current hart reservation.
The architectural contract only requires a nonzero failure code; portable software should not depend on a specific nonzero value.
aq is bit 26 and rl bit 25. SC.aq without rl is not guaranteed stronger ordering than both bits clear. SC.rl supplies release for the LR/SC sequence, limited to the accessed address domain.
rd=x0 discards only status writeback, without canceling the conditional store or reservation invalidation.
Common Usage Scenarios
LR/SC conditional update
SC.W supports LR/SC conditional updates; software checks rd for zero/nonzero, and a valid reservation does not guarantee success.
Pre-Use Checklist
Syntax Check
- Use rd, rs2, (rs1), with no offset; funct5=00011, and aq/rl are separate ordering bits.
Semantic Check
- Confirm Zalrsc or A, a reservable writable region, and natural alignment; SC.D is RV64-only.
- Success stores data and returns rd=0; failure performs no data store and returns nonzero, with reservation invalidated in both cases. A valid reservation does not guarantee success; failed implicit translation/protection side effects are unspecified.
Pitfalls / Common Confusions
The address must be naturally aligned to 4 bytes; misaligned SC raises address-misaligned or access-fault.
A valid reservation is necessary but does not guarantee success; software should check rd.
Failure code 1 means unspecified failure; portable software assumes only a nonzero failure code.
Eventual progress applies only to constrained LR/SC loops meeting code, matching address/size, and region eventuality conditions.
FAQ
Does SC.W modify memory on failure?
A failed SC performs no data store, writes nonzero status (discarded for rd=x0), and invalidates the reservation. Side effects of implicit translation/protection accesses are unspecified.