SC.W
RISC-V SC.W Instruction Details
Instruction ManualR-typeConditionally store 32-bit word to address in rs1: writes rs2 only if reservation holds, rd gets 0 (success) or nonzero (fail)
Instruction Syntax
sc.w rd, rs2, (rs1)
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
AZalrscAtomic
Related Search Terms
Instruction Behavior
SC.W conditionally writes the word in rs2 to the address in rs1. Succeeds only if the reservation from the most recent LR.W is still valid and the reservation set contains the bytes being written: writes rs2 to memory, writes zero to rd. On failure, does not write memory, writes nonzero to rd. Invalidates any reservation regardless of success. Supports rl bit for release semantics.
Common Usage Scenarios
Atomic & Sync
Understand this scenario with real code like «sc.w.rl t0, a1, (a0) # try store a1 to *a0 with release ordering, t0=0 on success».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
May spuriously fail, requires retry loop
Only check failure code for non-zero, don't depend on specific value
Code between LR/SC must follow constrained LR/SC loop rules
Address must be 4-byte aligned