Is FCVT.D.LU available on RV32?
No. The official F/D conversion rules define the L/LU 64-bit integer forms as RV64-only.
FCVT.D.LU
RISC-V FCVT.D.LU Instruction Details
Instruction ManualR-typeRV64 unsigned 64-bit integer-to-double precision conversion, rounded by rm/frm and written to FP rd.
Instruction Syntax
fcvt.d.lu rd, rs1, rm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
DFloating-Point Convert
Instruction Behavior
FCVT.D.LU is an RV64-only integer-to-floating-point conversion. It converts the unsigned 64-bit integer in x[rs1] according to rm to double precision and writes f[rd]; NX is set when the target FP format cannot represent the value exactly.
FCVT.D.LU Decode And Execute Animation
Shows the D-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, rm rounding, read the integer source, then write the floating-point destination.
rd
rs1
rm
fcvt.d.lu
,
,
Execution Context
fmt=D (01)
rs2=LU
rounding: RNE nearest-even
fflags: 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
11010
FCVT.D
01
fmt=D
00011
rs2=LU
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xD2358553
opcode
1010011 -> OP-FP
funct5/fmt
11010 + 01 -> FCVT.D.LU
rs2
00011 -> LU source
rm
000 -> RNE nearest-even
rd/rs1
fa0(f10) / a1(x11)
read
a1(x11) = 0xFFFFFFFF (4294967295)
convert
uint64 0xFFFFFFFF (4294967295) -> D 4294967295.0
write
fa0(f10) = 4294967295.0; 0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; FCVT conversion instructions use opcode 1010011.
encoding: 0xD2358553
syntax : fcvt.d.lu fa0(f10), a1(x11), rne
result : fa0(f10) = 4294967295.0; 0
The current 64-bit integer example is exactly representable as D format, so example fflags remains 0.
FCVT Conversion View
LU source
0xFFFFFFFF (4294967295)
conversion
uint64 0xFFFFFFFF (4294967295) -> D 4294967295.0
writeback
fa0(f10) = 4294967295.0
The current 64-bit integer example is exactly representable as D format, so example fflags remains 0.
This animation shows only D-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
Quick Understanding & Search Notes
fcvt.d.lu is an RV64-only FCVT.D.LU form: it reads an unsigned 64-bit integer from integer rs1, converts according to rm/frm to double precision, and writes FP rd.
OP-FP opcode is 1010011; funct5=11010 denotes integer-to-FP FCVT.
fmt=01 denotes the double precision destination format; rs2=00011 selects LU as the integer source, not a normal second source register.
rd is an FP register and rs1 is an integer register; large 64-bit integers may set NX when the target FP format cannot represent them exactly.
This L/LU form is RV64-only; RV32 pages should not present it as an available instruction.
Common Usage Scenarios
Type Conversion
Understand this scenario with real code like «fcvt.d.lu f0, x10, rne # f0 = (double)(ulong)x10 (RV64)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
L/LU forms are RV64-only; do not use them on RV32.
rd is an FP register and rs1 is an integer register; the rs2 field only selects the L/LU format.
Double precision cannot represent every 64-bit integer; inexact results are rounded by rm and set NX.
The rm field may encode a static rounding mode; DYN uses fcsr.frm.
FAQ
Which register classes do rd and rs1 use in FCVT.D.LU?
This is an integer-to-FP conversion: rd is an FP register and rs1 is an integer register.
What does the rs2 field mean in FCVT.D.LU?
The rs2 field selects the LU unsigned 64-bit integer format; it is not a second source operand in assembly syntax.